No -- SI people are all loopy.
> Sorry, ...couldn't resist.
Lines like that should be deposited -- they leave people sputtering.
> Anyhow,
> that sounds great! How much C are you going to add and where on the
> chips do you plan put it? The I/O ring, core, ...?
Currently there's a capital appropriation going through for hammers.
After that, it's whatever fits wherever we can get it. It's really
a methodology issue, but the fact remains that onchip capacitance
has far higher Q and less distribution parasitics than anything
off-chip can approach.
Here's a general idea:
For a synchronous design, CMOS power dissipation is pretty much
a capacitive-discharge effect. A device that burns 2400 mW at
3.6v and 100 MHz has an effective load capacitance of about 2000 pF
mostly right after clock events. If we go with a 10% supply dip,
that means bypass of 20 nF; a gate capacitance of 6-7 mF/sq.M gives
an area of about 3 square millimeters. NOT small, but not huge
either; it's about 10% of a typical IC.
Keep in mind that quiescent CMOS gates provide distributed
capacitance via their input capacitance, both by coupling to
the supply rails of the devices driving them and by the series
capacitance of their own input transistors. (This isn't anything
like 10% of the die area, but it is enough to make a difference
and has the nice characteristic of random interconnect.)
The challenge to people like me is to change our methodology
to at least take advantage of the available floorspace to add
caps without pushing out development time. It's frustrating
partly because in deep submicron designs the routing takes up
so much of the die that there is quite a bit of silicon doing
nothing but supporting oxide.
> >The other possibility is that people like me(!)
> >will incorporate termination onchip (as the Creator intended it) to
> >eliminate stubs and add capacitors onchip (on the RIHGT side of
> >bondwire inductance.)
-- D. C. Sessions [email protected]