[email protected]
Fri, 31 Oct 1997 08:15:48 -0500

I agree that great care should be taken when designing a high speed
system using Spread Spectrum Clock Generators (SSCG). However, this
technique is a powerful tool to reduce the cost of products. Lets
say you have a system that has a 100MHz to 300MHz processor that
uses a PLL to multiply a 66MHz clock to run the core. This system
also has a chip set that also uses a PLL. The clock period changes
by 3ps or less on a cycle by cycle basis (excluding VCO jitter present
in all synthesizers). If the PLL closed loop bandwidth is >=3MHz
one would expect the increased skew between the clock and
core to be <500ps worst case (higher PLL bandwidth the lower the skew).
You should simulate and test the design and if your system has
enough skew margin then you should be in business.

See "Design Considerations of Phase-Locked Loop Systems for
Spread Spectrum Clock Generation Compatibility,
1997 IEEE EMC Symposium." (can be down loaded from

Now, what if you have to redesign the PLL's and spend $100K to $500K
of NRE. If you save $5 to $20 per product, because you did not need
expensive shields, gaskets and high dollar PCB material, a high volume
product could save millions of dollars. If you are designing future
products and plan the design with SSCG in mind then you can reduce
NRE costs.

SSCG is a source reduction technique and good PCB design reduces
the "GAIN" of the antennas in a system. Put the two together and reduce
the shielding costs and weight of your product.

Finally there are some systems where SSCG should not go! One example
is in communications where a fixed frequency is required. Another
is where a real time clock is needed to control a process with
absolute time requirements.

Dr. Keith Hardin
Senior Engineer
Lexmark International Inc.
740 New Circle Rd NW
Lexington, KY 40511

Having been both an EMI engineer for many years as well as a designer of
high performance interconnects, I have to make a comment about jittery
This is an invention of the EMI community and the bane of most high
performance designers when trying to meet timing requirements. Controlling
emissions from clock lines should be done by proper board and signal
integrity design, not spread spectrum techniques. The amount of problems
introduced in a 100 MHz system by introducing enough jitter to make a
difference in the spectral content of the clock spectrum is overwhelming.
If you are designing a garden variety bus (VME, FutureBus, etc.) you should
be able to control the emissions with good PWB design.
ed sayre
At 12:38 PM 10/29/97 +5:30, you wrote:
>A WEB source suggests that:-
>In order to reduce EMI, there should be some logic that introduces a
>jitter into the clock network. This results a pulse energy to spread
>horizontally in the frequency domain which inturn results in the
>quasi-peek energy reduced. This will cause the resultant average
>frequency reduced slightly.
>Could anybody please explain what does this mean? Will it help? If
>so, where do I get more deatiled information about this?
>Thanks for your attention,
>Manix Velu.
>E-Mail: [email protected]
>Shuttle Technology Ltd.,
>32, St. Therese Street,
>Pondicherry - 605001,
>Office Telephone : 91.413.62301
>Residence Telephone : 91.413.40535
>Facsimile Number : 91.413.62095
>DISA Office Telephone : 91.413.62099 <wait for intercomm tone> <press*>

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