Re: [SI-LIST] : Modeling connector pin vias

Mike Jenkins ([email protected])
Wed, 29 Oct 1997 13:17:55 -0800


I don't know if this is part of _______........._____
what you're looking for, but one / \ area /
can estimate lumped capacitance / \_____/
from a TDR trace by measuring or /
estimating the area of a negative /
reflection due to the capacitance. /
This area is Z0*C/2, where Zo is ___/
the line characteristic impedance.

By the way, if one replaces "negative" by "positive" reflection,
shunt capacitance by series inductance (a connector, for instance),
and Zo*C/2 by L/(2*Zo), one can estimate parasitic inductance, L.

These formulas are exact, & based on the LaPlace Final Value Theorem.


 Mike Jenkins               Phone: 408.433.7901            _____     
 LSI Logic Corp, ms/G750      Fax: 408.433.2840        LSI|LOGIC| (R)   
 1525 McCarthy Blvd.       mailto:[email protected]        |     |     
 Milpitas, CA  95035      |_____|