Re: [SI-LIST] : Can floating data bus cause DRAM soft errors?

L D Miller ([email protected])
Wed, 01 Oct 1997 14:51:10 -0700

That should be easy to test: just tack some pullups on.

Larry Miller
Bay Networks

At 07:33 PM 10/1/97 +0200, you wrote:
>Hello all,
>I know that SI issues (noise, non-monotonic edges) can readily
>cause DRAM errors, but none of the usual candidates seem to be
>the source of the problem I'm trying to fix..
>My precise question concerns the effect of a slow-rising
>data bus. But first, a brief rundown on the background to
>the question:
>We have a board which has two identical DRAM memory systems:
> - same type of address buffers
> - same type of ASIC for data buffering
> - same type of controller (control signals)
> - same number/type of memory devices
> - same routing (my opinion)
>One memory system (A) has many more errors (x100) than the other (B).
>The errors are "soft" and only a single bit is in error each time.
>On average, a board will have a soft error every 6 months.
>Obviously, alpha particles cannot explain all these soft errors.
>All the timings are OK. The refresh (CBR) is OK.
>That leaves SI, which is my job....
>I've checked and double checked, but all the signals
>are noise-free, with nice clean edges.
>One of the few leads - and its a long shot - is as follows:
> A difference between the two memory systems is that the data bus
> of memory system A is left in a high impedance state for
> much longer intervals (10's of microseconds) than system B.
> So the signal level is more likely to float into the input
> threshold zone of the memory and the ASIC.
>So my question is:
> Can a floating bus create enough noise inside a memory device
> to give rise to a soft error?
>Thanks in advance for any comments/advice,
>John Fitzpatrick <[email protected]>
>Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France
>Tel: +33(0) Fax: +33(0)