Re: [SI-LIST] : Burst noise simulation

[email protected]
Wed, 17 Sep 1997 01:13:28 -0400 (EDT)

Si-List, Bernhard,

You ask about BURST interference. Is your interference from a current device
such as a resistor or from a piezoelectric component such as a capacitor or
quartz oscillator? In resistors, it depends on the type of resistor. Carbon
composition resistors can have as much as +10 dB of noise while metal foil
has the lowest noise (typically -40 dB). The number of burst occurances and
their voltage level is related to the current through the resistor and
increase with increasing current. The mechanism for burst noise in
piezoelectric components is much more complicated but is usually related to
sudden temperature shifts or mechanical mounting stress.

Resistor or capacitor burst noise can be modeled with a random narrow
positive and negative voltage pulse generator -- random in occurance and
pulse height. Piezoelectric burst noise is modeled by adding a random narrow
voltage pulse to the low state of a clock oscillator with an amplitude equal
to the clock signal (it will look much like a glitch).

Please be more specific in what you need.

Harold Snyder


In a message dated 97-09-12 12:12:57 EDT, you write:

>> Subj: [SI-LIST] : Burst noise simulation
>> Date: 97-09-12 12:12:57 EDT
>> From: [email protected] (Unger Bernhard)
>> Sender: [email protected]
>> To: [email protected] ('SI_forum')
>> Does anyone have experience with simulation of BURST-interference?
>> How can I model coupling of BURST to tr-lines on PCBs or cables?
>> Does there exist tools for simulating the BURST-interference?
>> Are there any papers or books which covers this issues?
>> Any information would be helpful.
>> Thanks in advance.
>> Bernhard Unger >>

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