Re: [SI-LIST] : SSO in ASICs

Robert Tsai ([email protected])
Fri, 22 Aug 97 11:21:58 MST

I agree with John 100%. The same question has been bothering me for a long time.

More fundermentally, if we don't apply any load to an output driver or apply just resistive load, the edge rate of today's drivers seems to be very fast at 600psec or less. Based on some fundermental knowledge of signal integrity, we should use transmission line models instead of lumped capacitance models for all interconnects with length longer than say, 1cm. Therefore, the commonly used loads in many data books and simulation of 50pf, 100pf loading are incorrect. These loading approach may be adequately accurate when channel length was larger than 1 micron and drivers were slow (edge rate was slower than the interconnect delay). But one should not use the same lumped load for today's drivers. Am I right?

If we have to use transmission line model for the interconnects. The only thing could affect SSO will be the impedance of the line. The length of the line does not directly affect SSO, except through reflection noise (assuming the length of the line is longer than 1/2 of driver edge rate). But that is a different topic.

My humble little opinion. Please comment.


Chi-Taou Tsai