[SI-LIST] : PCB Benchmark '98

Pete Waddell ([email protected])
Thu, 21 Aug 97 13:09:15 -0800

I've been asked to send this in an ASCII format, so here it is.


The following is a call for comments regarding the 1998 PCB Benchmark
to be held at the PCB Design Conference in Santa Clara, CA. in March
1998. If you are not the person to comment on this please pass it on
to the pertinent person. Responses received by September 8, 1997 will
be considered.

Thank you for your participation.
Pete Waddell


The PCB Benchmark is divided into three individual phases:
Phase 1 - Task Grading
Phase II - Design is placed and routed
Phase III - Finished design is sent to a local fabricator for
overnight build.

Phase I
Phase 1 is divided into two divisions. Division 1 is comprised of
capabilities that all PCB schematic and layout tools should
incorporate. All participants will be graded on division 1 tasks.
Division II, based on more sophisticated capabilities is optional.

The Benchmark uses a task driven methodology wherein participants are
asked to accomplish (and are graded on the ability to accomplish)
specific tasks. These tasks are developed by EDA users. Every effort
is made to eliminate any specific methodology from each task.

In the past tasks have been grouped by categories. A category is a
general area of capability such as Signal Integrity or DFM etc.. Each
grader is responsible for one category, and grades all participants
within that category.

If the task can be accomplished a point is awarded. If not, no point
is awarded for that task. There are no partial or fractional points,
and there are no deductions for not having a certain capability.
An example of a task could be

display schematic and layout.
On schematic, highlight/select net D12.
Is net D12 highlighted on layout? (1 point for yes) ____

On layout highlight/select D11.
Is D11 highlighted on schematic? (1 point for yes) ____

Another task might ask the participant to:

Interactive route editing
Interactively route net D11 on layers 1 and 2.
Does system display aggregate trace length during route? (1
point for yes) ____
For each layer? (1
point for yes) _____
Route D1-D8.
Display report that shows total length for each net ( 1
point for yes)

Graders are encouraged to make comments on each system's ability to
handle the specific task they are responsible for. These comments will
be posted, but are not part of the grading.

Grades will be posted, as they are collected, on PCDmag.com ,
(Printed Circuit Design's web site), which will be live at the
conference. (there will be several terminals located on the exhibit
show floor).

Phase II
An x/y location list is provided. Participants may use this list, or
their own autoplacement tool. Layout is then autorouted (time and
completion rates are recorded), a fab package is submitted to
coordinators.(requirements are spelled out in a design and fabrication
document provided prior to the event)

Phase III
1. Fab packages will be submitted (blind) to the fabricator who will
provide a post-mortem report on each package. The fabricator will not
know which vendor submitted the package. Finished boards will be on
display on the exhibit floor, during the final day of the show, in
PCD and on PCDmag.com

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