Dear John Lin,
The number of the power/ground pins depends on the allowable ammount of
simultaneous switching noise (SSN) in the supply pins of the circuit. This
swiching noise can be produced by the internal circuitry and/or by the
output drivers. First you may estimate the amount of SSN of the internal
circuitry in a worst case (i.e. for the maximum activity). Then you have to
analise the SSN generated by an output driver and perform a computation of
the SSN produced when all the output drivers switch simultaneously in the
same direction. Usually this is the main source of SSN and you can ignore
core logic SSN. You can use the models of R. Senthinathan and J.L Prince
published in the book 'Simultaneous Switching Noise of CMOS Devices and
Systems' from Kluwer Academic Publishers. You have to take into account
that the amount of noise is not directly proportional to the number of
simultaneous switching drivers (there is some amount of negative feedback
that limits it). Then you can compute the number of power pins by finding
the maximum allowabel effective inductance (SSN is proportional to
Leff*di/dt). A raw estimate of the Leff is found dividing the typical or
mean autoinductance of a pin of your package by the number of power pins.
A more precice value can be obtained with accurate package models or FEM
simulation taking into account mutual inductance between near pins. You can
try, for exemple, 'A Simultaneous Switching Noise Design Algorithm for
Leadframe Packages with or without Ground Plane' by Chender Huang, Yaochao
Yang and J.L. Prince in IEEE Trans. on Components, Packaging and
Manufacturing Technology-Part B, Vol.19, No. 1. February 1996.
I hope this helps you!
Jose Luis Gonzalez
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