I have personally seen the serious effects of perforated webs on a fast edge
TAXI chip that completly interrupted the I/O operation of a complete board.
The problem is just as bad for fine pitch surface mount devices and
connectors. Consider daughter cards mounted in surface mount 50 mil
connectors. If you line up the vias in a row because "neatness counts" the
effect will be to bisect the board. If the effect shows up at EMI test
time, very significant engineering re-design and material loss will be
suffered with the slip in schedule. This is the best reason for experience
in Signal Integrity and EMI to be in the same head.
Sincerely,
ed sayre
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| NORTH EAST SYSTEMS ASSOCIATES, INC. |
| ------------------------------------- |
| "High Performance Engineering & Design" |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| Dr. Ed Sayre e-mail: [email protected] |
| NESA, Inc. http://www.nesa.com/ |
| 636 Great Road Tel +1.508.897-8787 |
| Stow, MA 01775 USA Fax +1.508.897-5359 |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+