Re: decoupling/ bypass capacitors at connectors

[email protected]
Tue, 4 Mar 97 14:16:16 -0800

Lary wrote:

>>>>>This is a very important discussion on the role of
decoupling capacitors near connectors. It is surprising how
few people understand that return current ALWAYS travels on
the adjacent reference plane, regardless if it is vdd or gnd
or which way the signal happens to be switching (high or low).

The return current will travell on all adjacent structures! it may be that
if there is only one plane below it then yes, most will be on that plane
and a little bit on adjacent traces. but if it is sandwiched between two
planes then proportional currents will flow in each plane.

>>>>>>To extend this discussion, don't we have the same situation with a
via that goes through a multi-layer board? This is especially true if the
board has many layers including a pair of power/vdd planes near the top of
the board and a pair near the bottom of the board. There may even be
a field of vias where a wide bus makes a transition from one side of a
board to another. This is beginning to look a lot like a connector.

Vias are the death of impedance control. minimize vias or minimize their
effect by clever design.

>>>>>>Decoupling between the power pairs will be important, just as in
the connector example below. I like to stitch all of the ground
planes together with a via in every square inch of the board, then
decouple each power plane often, all over the board. I haven't done
the hard
analysis for this, but my feeling is that this should be good for .5 nSec
rise times. Any comments?

For 0.5ns requirements, the stitching has no effect except immediately
adjacent to the signal trace or connectors. The displacement current will
find the most proximal structure to propagate the image current.

Hans Mellberg