Is there a reason for not altering your stackup to yield similar impedances on
all layers? It will be tough to avoid reflections with that big of a
discontinuity in your trace. A series termination at the source may help to
some degree.
Brad
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Brad Mendenhall [email protected]
BroadBand Technologies, Inc. Phone: (919)405-4682
4024 Stirrup Creek Drive FAX: (919)544-5356
Research Triangle Park, NC 27709-3737
> From /DD.id=0139127/G=Norman/S=Wong/@nt.com Sat Apr 20 14:06 EDT 1996
> Date: 19 Apr 1996 16:55:25 -0400
> From: Norman Wong <[email protected]>
> Subject: SI- Termination Comments Wa
> To: Signal Intergity Group <[email protected]>
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> Subject: Time:3:44 =
> PM
> OFFICE MEMO SI- Termination Comments Wanted =
> Date:4/19/96
>
> I am currently working on a mid-speed (<50MHz) digital circuit pack and =
> would like to proper terminate some long lines(up to 15 inches). It =
> consists of CPU, DSP, SRAM, Flash etc. I am approaching the problem by =
> using Daisy-Chained tracks and AC terminations. There are some findings =
> that I would like your comments:
>
> 1. When using uncontrolled-impedance FR4 PCB, based on my calculation on =
> a 6 layer board, the micro-strip (8 mil) Z0 is about 75 Ohm and the =
> micro-strip Z0 is about 45 Ohm. That means a mismatch every time I =
> switch layers. Does anyone has experience on this? Does it matter for 5 =
> ns rise time? How about 1ns rise time?
>
> 2. My EDA simulation package showed that after termination, my signals =
> do not look much cleaner. In fact, it look worse and seems to be loaded =
> down (Vpeak is about 3.5-4V instead of 5V). Does this make sense?
>
> 3. At want point could I use T instead of Daisy-Chain so that the stub =
> look like capacitance, no transmission lines? A lot of time daisy chain =
> line is longer than a treed line.
>
> All comments on this matter are welcome.
>
> Thank you.
>
> Norman Wong
> Hardware Design Engineer
> Nortel, Wireless Development Center, Calgary
>
>
>