Re: component overstress

Don Abernathey ([email protected])
Mon, 11 Mar 1996 15:03:12 -0800


On Mar 11, 2:43pm, Arthur Collard wrote:
> Subject: Re: component overstress
> On 11 Mar 96 15:04:28 George Stevens writes:
> >
> > I am currently investigating a phenomenon that is occuring associated
with 64k
> > x 4 Srams
> > from Quality Semiconductor. Field failures are occuring characterized
> > component failures,
> > which, when a Failure Analysis is completed by the manufacturer, finds an
> > open and
> > carbon deposits observed on Vcc and ground pins. This, reportedly,
> > high current draw
> > caused by "overstress" in our application. I am currently attempting to
> > measure over/undershoot
> > and voltage spike anomolies on the board but have found nothing that
> > the manufacturers
> > spec yet. I have been told that contention can also overstress an input,
> > assume when two or
> > more drivers attempt to pull the input to the Sram low. Is this
> >
> > Anybody have any history on this device or ideas on what other signal
> > may cause an overstress
> > on an input stage?
> I have seen this type of problem many times it's called latchup. This can
> caused by an overstress at an input, output or I/O pin. The latching
> is inherant to CMOS devices and is usually triggered by excessive voltage.
> designs protect against +/- 7 volts and +/- 100mA static however the pulse
> latchup testing is a better test.
> The place where the latchup mechanism is initiated from does not
> damage. The damage is usually where the latching currents flow to and from
> namely power and ground metal and associated junction contacts. I put a
> together of items external and internal to the chip which would cause this
> happen.
> Latch-up trigger mechanisms:
> External trigger mechanisms
> Ringing (over shoots) - Poor design.
> System noise
> System power-up and power-down
> (if inputs are generated from a different supply).
> Forward biased junctions at input/output pins
> V at input > Vcc
> V at input < GND
> Worst at elevated temperatures.
> Internal Chip trigger mechanisms
> Forward biased junctions on chip - design, layout, device.
> Impact ionization - design
> C dV/dT current - design, layout, external noise
> Punchthrough current - device, process
> Field inversion - process
> Junction leakage (light) - process
> Defects (fab and reliability failures)
> Hope this is helpful.
> regards
> AC
> --------------------------------------------------------------------------
> | M O T O R O L A - Advanced Microcontroller Division (AMCU)
> | ------------------------------------------------------------------------
> | Art Collard Modular Circuit Design email:
[email protected]|
> | ------------------------------------------------------------------------
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>-- End of excerpt from Arthur Collard


I have have had Component Engineers tell me that we must have some
serious electrical overstress occurring in our systems because of
failure analysis reports from vendors. The CE's reasoned that the
failure analysis report was the "smoking gun" that pointed to a
problem in the DC (+5v, +3.3v) power distribution system. This, by the
way, was in designs where the signal integrity was excellent.

To say that I've been skeptical is an understatement.

I have had long discussions with a CE about the difficulty of creating
localized (to an individual IC on a circuit board) power spikes that
could cripple an IC so that it would eventually fail. My own
investigation has led me to believe that manufacturing processes are
much less controlled, and much more likely to cause latent failures
which come back as "electrical overstress". A complete review of the
material flow from vendor to customer is necessary.

On an SRAM specific note: Usually if your signal integrity
(i.e. over/undershot) is bad enough to cause latchup, you will see a
higher than normal soft-error rate. The current injected into the
substrate can cause other failures before latchup.

Thank you |
Don Abernathey |
(503)690-6234 |
[email protected] |