Re: component overstress

Greg Edlund ([email protected])
Mon, 11 Mar 1996 15:46:26 -0600

>Errors-To: [email protected]
>Errors-To: [email protected]
>Date: Mon, 11 Mar 96 14:43:31 CST
>From: [email protected] (Arthur Collard)
>To: [email protected], [email protected]
>Subject: Re: component overstress
>Cc: Jim_Thrasivoulos/[email protected],
> Goodarz_Goodarzi/[email protected]
>X-UIDL: 826578641.000
>On 11 Mar 96 15:04:28 George Stevens writes:
>> I am currently investigating a phenomenon that is occuring associated
with 64k
>> x 4 Srams
>> from Quality Semiconductor. Field failures are occuring characterized by
>> component failures,
>> which, when a Failure Analysis is completed by the manufacturer, finds an
>> open and
>> carbon deposits observed on Vcc and ground pins. This, reportedly,
>> high current draw
>> caused by "overstress" in our application. I am currently attempting to
>> measure over/undershoot
>> and voltage spike anomolies on the board but have found nothing that
>> the manufacturers
>> spec yet. I have been told that contention can also overstress an input, I
>> assume when two or
>> more drivers attempt to pull the input to the Sram low. Is this possible??
>> Anybody have any history on this device or ideas on what other signal
>> may cause an overstress
>> on an input stage?
>I have seen this type of problem many times it's called latchup. This can be
>caused by an overstress at an input, output or I/O pin. The latching mechanism
>is inherant to CMOS devices and is usually triggered by excessive voltage. Most
>designs protect against +/- 7 volts and +/- 100mA static however the pulse
>latchup testing is a better test.
>The place where the latchup mechanism is initiated from does not necessarily
>damage. The damage is usually where the latching currents flow to and from
>namely power and ground metal and associated junction contacts. I put a list
>together of items external and internal to the chip which would cause this to
> Latch-up trigger mechanisms:
> External trigger mechanisms
> Ringing (over shoots) - Poor design.
> System noise
> System power-up and power-down
> (if inputs are generated from a different supply).
> Forward biased junctions at input/output pins
> V at input > Vcc
> V at input < GND
> Worst at elevated temperatures.
> Internal Chip trigger mechanisms
> Forward biased junctions on chip - design, layout, device.
> Impact ionization - design
> C dV/dT current - design, layout, external noise
> Punchthrough current - device, process
> Field inversion - process
> Junction leakage (light) - process
> Defects (fab and reliability failures)
>Hope this is helpful.
> --------------------------------------------------------------------------
>| M O T O R O L A - Advanced Microcontroller Division (AMCU) |
>| ------------------------------------------------------------------------ |
>| Art Collard Modular Circuit Design email: [email protected]|
>| ------------------------------------------------------------------------ |
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>| Motorola - Advanced Microcontroller Division |
>| 6501 William Cannon Drive West, Austin, Texas 78735-8598 |
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My two bits:

I believe latch-up is defined as a positive feedback
mechanism which has its origins in a parasitic SCR
(silicon controlled rectifier), which is a sandwich
of p-n junctions arranged in this order: p-n-p-n.
I'm not sure about how you get the positive feedback...

If you had a bus contention problem, I think you'd
expect to see a power pad toasted on one chip and a
ground pad toasted on another chip. You can also have
problems with a 5 V device and a 3.3 V device trying to
drive the same line high. Sounds like a power and a
ground pad toasted on the same chip would lead you more
toward the latch-up hypothesis.

Greg Edlund                o---/\/\/\---+-----+---o
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