drivers, recivers and power planes

Larry Smith ([email protected])
Mon, 26 Feb 1996 12:01:42 +0800

I have been following with great intrest the recent discussion on impedance
across ground planes, and Vias & decoupling. Perhaps an example will clear
some things up -or- create some more controversy. Consider two CMOS chips
on a PCB, one driving and one receiving. Let the PCB have 6 conductor
layers defined as:


There are three distinct environments on this card: the drivers, the
transmission lines, and the receivers.

1) The driver chip will either take current from the local power rail and
put it on a transmission line; or it will take current from a
transmission line and sink it to ground (low-to-high or high-to-low
transition). In each case, decoupling will help to maintain the local
power supply (the power supplied to the silicon transistors) at a
constant potential difference. For the 1st nSec or so, the power supply
current comes from the on-chip parasitic capacitance. Over the next
several nSec, current comes from the PCB power plane capacitance, then
local ceramic capacitors, then bulk (possibly tantalum) capacitors, and
eventually from some switching power supply as time constants time out.
It probably takes 10,000 nSec or longer before the switching power
supply responds, so decoupling capacitors are supporting the switching
activity for a very long time.

2) The transmission line environment becomes important shortly after the
driver makes a transition. In every case, the return current for the
transmission line trace will be on the nearest plane. for S1 and S2
traces, this will be the power plane. For S3 and S4 traces, this will
be the ground plane. For this PCB stackup, the nearest trace controls
the impedance of the transmission line. A current will be either
sourced onto, or sunk from the transmission line according to the
the power supply voltage, driver impedance, transmission line impedance
and Ohm's law (simple voltage divider). This current will continue
to flow until a reflection comes back from some discontinuity or the
far end of the line.

Note that current may or may not have come from a decoupling capacitor
depending on the direction of transition and the refrence plane for
the transmission line.

3) At the receiving chip, a transition will eventually occur. It is likely
to be several nSec after the driven signal, depending upon the trace
length. The voltage on the trace will be with-respect-to ground if the
trace is on S3 or S4; and WRT power if the trace is on S1 or S2. This
may be for the 1st several hundred pSec if the trace is coming from a
nearby via, or for several nSec if the trace stayed on one layer all
the way from the driver. Eventually, after all the transients have
settled out, the voltage at the reciever will be the same as the
driver output WRT it's local reference (power of ground).

Now consider a stackup with more signal and power layers:


Things get a little more complicated on the burried layers (S3 & S4) because
the impedance of those layers is controled by both power and ground planes,
and return currents flow on each plane, but the priciples are the same. As
discussed by Andy at Dec, there are some interesting dynamics when signals
pass between layers (ie S1 to S6).

> And yet, consider a via from one outer layer to the other outer layer
> (as a worst-case scenario), with a number of intervening reference
> planes. The return current of the transient edge, runs under the etch
> on the first layer until it reaches the via anti-pad; and then it seems
> to have nowhere to go! It spreads out around the via, finding an
> increasing capacitance to the next reference plane down; and then to
> the next plane; and so on, until it reaches the bottom reference plane,
> where it re-forms as the mirror current under the etch there. If you
> have picosecond edges, this is something to worry about. It's somewhat
> similar to running etch over a reference plane split.

In this situation, it is useful to add vias between Gnd layers. For 1 nSec
rise times, I have suggested to our physical design group that there should
be a ground-plane-stitch-via on every square inch of the PCB. This
guaruntees that there is a path for the return current that is 1/6 of a rise
time long, in addition to the capacitance mentioned by Andy.

Editorial note - you may have noticed that my email address no longer has in it. I have 'seen the light' and now work for Sun Microsystems.
I actually sit in the same office as Ray Anderson and will be helping him
maintain this si-list.

Larry D Smith