On an area efficiency basis, ceramic SMT bypass capacitors provide excellent
solutions, but one has to chack the semi-conductor manufacturers
recommendations of 0.01 uF or other such wide ranging rules against the
types of parts present, rsietime, routing, perforation density etc. etc. It
requires a lot more than simple application of general design rules.
With regard to modeling and simulation, formation of circuit elements of the
physical structures is what interconnect characterization is all about. This
is a large part of what NESA does day in and day out and it is a skill
learned by experience and verified by measurement.
ed sayre
P. S. The complexity of the subject is an excellent reason for not making
major system decisions on the basis of suppliers heresay data.
-------------------------------------------------------------------------
At 04:38 PM 2/23/96 PST, you wrote:
>
>Text item:
>
>
>
>I agree with Ed's conclusions from a systems point of view but what happens
>internal to a multi layer high speed board always leaves me with a slightly
>unclean feeling.
>
>Consider a board stackup that has signals referenced against both ground and
>power planes. from an AC point of view the power planes are as good as
ground.
>If the signal is driven in reference to that plane (usually not the case) it
>will work fine. If the signal is ground referenced, and uses the power plane
>for impedance control, it will work fine if the plane is decoupled to the
>driver's reference electrically close to the driver and to the receiver. Now,
>if the signal is routed via vias in a dense board to use multiple power and
>ground planes as its reference, how do I assure or even model signal integrity?
>
>One suggestion is that at each via, a matching ground to voltage plane
>decoupling cap be added. Any ideas?
>
>Tomm
>______________________________ Reply Separator
_________________________________
>Subject: Re: Re[2]: impedance across ground plane
>Author: [email protected] at SMTPGATE
>Date: 2/23/96 5:01 PM
>
>
>Barry:
>
>In the design of high performance digital circuits, read that as maintaining
>specified edge rates for clock rates >40 -50 MHz, the concept of earth
>ground never comes into the equation. The gentleman from the University of
>Missouri, Prof Hubing, is exactly correct, namely that currents return to
>their source. This is just another way of saying that the sum of the
>voltages around a loop is zero and the sum of currents at a node is also
>zero. Energy returns either by direct conduction, ie. currents or through a
>coupling field.
>
>The concept of earth ground vs. logic return ground is of course confusing.
>In some equipment, especially in the European telephony area, chassis ground
>and logic ground MUST be isolated. In the computer industry, the golden
>"single point" ground has been the EMI model. Both these items are SAFETY
>related issues and have nothing to do with EMI compliance or for that matter
>impedance across a high performance PCB.
>
>However, both these are necessary to be taken into account if one wants to
>sell equipment on the world market. Specific solutions to the radiated EMI
>problem says that common mode voltages between the logic and chassis ground
>must be engineered to be as small as possible to meet the defined standard.
>One can achieve this by either tying logic ground to chassis ground by a low
>impedance connection. The single point ground meets this criteria, at least
>at low frequencies (small in the Length/lamda) sense. When the frequencies
>in question are higher and the signal spectrum is wider, then multi-point
>grounding becomes more popular. But its just the need to maintain connection
>densities that are small in the Length/lamda sense or equivalently small in
>the Area/lambda**2 for loops. This approach sort of guarantees that even if
>the system radiates, it does not do it well and the fields are evanescant
>(non-propagating) around the equipment.
>
>The alternative is to maintain no connection ie., current = 0 between the
>chassis (earth) ground and the logic ground. This is much harder to achieve
>since high frequency fields radiate and parasitically couple, particularily
>to cabling leaving the enclosed Faraday shield which one invariably
>constructs out of the chassis metal to contain the fields from the logic
>cards. This is a tough approach to enforce.
>
>What then is the story for signal integrity and EMI? One must keep the
>currents and logic fields confined to the logic cards. Recognize that power
>supply cables don't carry high frequency switching currents, so provide
>local energy storage in the form of bulk and properly spec'd high frequency
>bypass capacitors. Do not perforate the power and ground planes so
>thoroughly that the ASIC's and high density connector effectively cut the
>planes into sections. EMI and signal integrity problems come from such
>constructions. Check the finished artwork to see that the CAM process
>doesn't result in the same type of bisected planes condition. The board
>fabrication process wants bigger anti-pads than might be good for signal
>integrity and EMI system health.
>
>
>
>
>+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
>| NORTH EAST SYSTEMS ASSOCIATES, INC. |
>| ------------------------------------- |
>| "High Performance Engineering & Design" |
>+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
>| Dr. Ed Sayre e-mail: [email protected] |
>| NESA, Inc. http://www.nesa.com/ |
>| 636 Great Road Tel +1.508.897-8787 |
>| Stow, MA 01775 USA Fax +1.508.897-5359 |
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>Cc: [email protected]
>Subject: Re: Re[2]: impedance across ground plane
>From: "Dr. Edward P. Sayre" <[email protected]>
>To: [email protected] (Barry Ma)
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+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| NORTH EAST SYSTEMS ASSOCIATES, INC. |
| ------------------------------------- |
| "High Performance Engineering & Design" |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| Dr. Ed Sayre e-mail: [email protected] |
| NESA, Inc. http://www.nesa.com/ |
| 636 Great Road Tel +1.508.897-8787 |
| Stow, MA 01775 USA Fax +1.508.897-5359 |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+