MCMC '96 Advance Program

[email protected]
Wed, 17 Jan 96 20:17:51 EST

1996 IEEE Multi-Chip Module Conference
February 5--7, 1996
The Cocoanut Grove
Santa Cruz, California

Sponsored by:
* Circuits and Systems Society
* Computer Society
* Components, Packaging, and Manufacturing Technology Society
* Electron Devices Society

The 1996 IEEE Multi-Chip Module Conference (MCMC) will be held from
February 5--7 in Santa Cruz, California. MCMC is an annual conference
sponsored by the Circuits and Systems Society, the Components, Packaging
and Manufacturing Technology Society, the Computer Society and the
Electron Devices Society of the IEEE. The goal of this conference is to
bring together elements of packaging technology and design, circuits
and systems design, computer-aided design, modeling, analysis and
education. The conference is unique in its multi-disciplinary coverage
of all these aspects of MCMs.

This year's conference reflects recent strong activity in applications
of MCM technology. Increased system performance goals, coupled with
improvements in the costs and infrastructure for MCM technology, have
lead to greater use of the technology in product applications. Of
particular interest, is the increased activity in mixed signal modules.
This year's conference reflects that activity both in our keynote and
technical sessions. In addition, we have strong sessions in M
CM design
optimization (making Megachips in MCM technology), Infrastructure issues,
modeling, technology and Computer-Aided Design. An entire session has
also been devoted to flip-chip solder-bump, a technology that is enjoying
enormous interest of late.

This year's conference continues the trend started last year of adding
a poster session to our single track format. The papers selected for
the poster session are of a more specialized nature and, therefore,
have selective appeal. The Program Committee felt that this forum would
permit closer interaction among the presenters and their audience.

The conference program is oriented towards promoting interaction among
professionals in the MCM and related areas, and providing a forum for
presenting and discussing the latest developments, immediate needs and
future MCM trends. The conference will consist of two days of technical
sessions, invited talks, and a poster session, run as a single track so
that everyone may attend the entire program. In addition, February 5
will be a full day of tutorials providing in-depth coverage of
high-interest topics. There will also be exhibits and demonstrations
of state-of-the-art MCM prototypes and products from leading industrial
organizations and MCM CAD tools from universities and CAD vendors.

David B. Tuckerman Paul D. Franzon
Conference Chair Technical Program Chair

Conference Schedule

Monday, February 5, 1996


[8:30--5:00] Known Good Die
Larry Gilg (MCC)

[8:30--12:00] Chip-Size Packaging Developments
Robert Crowley, Thomas Goodman
TechSearch International, Inc.

[1:30 - 5:00] MCM-V (3-dimensional MCMs)
Peter Ivey and Jon Stern
University of Sheffield, UK

Tuesday, February 6, 1996

[7:00 - 8:30] Breakfast

[7:00 - 4:00] Registration

[8:30 - 8:40] Conference Welcome, David B. Tuckerman, General Chair

[8:40 - 9:20] KEYNOTE ADDRESS (Grand Ballroom)
The role of MCMs in Wireless Systems
Bill Baker, Baker Associates and Wireless Access, California

[9:20 - 9:50] SESSION I: Infrastructure Issues Discussion Session
Moderator: Steve Leanheart, GTE

[9:20 - 9:50] A Good Die is Hard to Find!
Jan Vardaman, TechSearch

[9:50 - 10:20] BREAK

[10:20 - 11:35] SESSION II: New MCM Applications
Moderator: Peter Ivey, University of Sheffield

[10:20 - 10:45] A Multichip Module Solution for High Performance
ATM Switching
L. Licciardi, M. Peretti, and L. Pilati, Centro Studi e Laboratori
Telecomunicazioni, Italy, and J.J. Ichai and F. Martin, IBM Montipellier
Technologies, France

[10:45 - 11:35] A Multichip Module, the Basic Building Block for
Large Area Pixel Detectors
K.-H. Becks, and P. Middelkamp, University of Wuppertal, M. Campbell,
E.H.M. Heijne, P. Jarron, G. Meddeler, L. Scharfetter and W. Snoeys,
CERN, J.-C. Clemens, P. Delpierre and D. Sauvage, CPPM/IN2P3/CNRS,
C. Gobling and R. Wunstorf, University of Dortmund, and L. Rossi, INFN Genova

[11:10 - 11:35] Space-Cube: A Flexible Computer Architecture
Based on Stacked Modules
Gary Bolotin, Jet Propulsion Laboratory

[11:35 - 12:35] LUNCH

[12:35 - 2:40] SESSION III: Flip Chip MCMs
Moderator: Y.C. Lee, University of Colorado

[12:35 - 1:05] Flip Chip: A Reliability and Cost Comparison with Wire-Bonding
Paul Magill, MCNC (Invited Paper)

[1:05 - 1:30] An Approach to the Low Cost Flip-chip Technology
Development with Punched-out Solder Disks by Micro-press Punching Method
H. Nakamura, M. Tago, M. Bonkohara, A. Dohya, and I. Morisaki,
NEC Corporation, Japan

[1:30 - 1:55] Fluxless Flip-chip for Multichip Modules
Julia L.F. Goldstein, Peter C. Kim, Belinda S. Fernandez and David B.
Tuckerman, nCHIP

[1:55 - 2:20] Thermal Evaluation of Multichip Modules for Flip-chip and
Wire Bonding Ceramic Packages
T. D. Yuan, IBM Microelectronics

[2:20 - 2:40] BREAK

[2:40 - 4:45] SESSION IV: Mixed Signal MCMs
Moderator: Heinz Blennemann, Silicon Graphics

[2:40 - 3:05]
Mixed Signal Digital Sub-Band Tuner Multichip Module
Ken Sienski, Calvin Field, Clint Schreiner and Mark Chivers, E-Systems

[3:05 - 3:30]
The Application of Silicon-on-Silicon MCMs to Advanced Analog Power Controllers
D. Dromgoole, A. Lotfi, A. Feygenson, R. Frye, and K. Tai, AT&T Bell

[3:30 - 3:55]
Integrated Microwave Filters in MCM-D
Philip Pieters, Steven Brebels, and Eric Beyne, IMEC, Belgium

[3:55 - 4:20]
A High Frequency, High Power Miniature based DC to DC Power Supply
Utilizing MCM-L Technology
Greg Miller and Matthew Salatino, Harris Semiconductor

[4:20 - 4:45]
A New Multichip-on-Silicon Packaging Scheme with Integrated Passive Components
Louis J. Guerin, R. Sachot, and M. Dutoit,
Swiss Federal Institute of Technology, Switzerland

[4:45 - 5:00] BREAK

[5:00 - 7:00] SESSION V: Poster Session
Moderator: Fabian Pease, Stanford University

[5:00 - 5:05] Introduction to Poster Session

[5:05 - 5:10]
A Cost Analysis Study of Deposited-MCM Active Substrates for
Testability Purposes
Joan Oliver, University Automoma of Barcelona, Spain,
and H. Kerkhoff, University of Twente, The Netherlands

[5:10 - 5:15]
Memory Hierarchy Organizations for MCM Architectures
D. L. Andrews, University of Arkansas

[5:15 - 5:20]
Flexible Access to MCM Technology via the Multichip
Module Designers' Access Service (MIDAS)
Jennifer Peltier and Wes Hansford, Information Sciences Institute

[5:20 - 5:25]
Development of a DSP/MCM Subsystem Assessing Low-volume,
Low-cost MCM Prototyping for Universities
P. Dehkordi, T. Powell and D. Bouldin, University of Tennessee

[5:25 - 5:30]
A Fast Method for the Simulation of Lossy Interconnects
With Frequency Dependent Parameters
Roni Khazaka, Michel Nakhla, and Q.J. Zhang, Carleton University,
Canada, and Juliusz Poltz, OptEM Engineering Inc., Canada

[5:30 - 5:35]
Determination of the Propagation Constant of Coupled
Lines on Chips Based on High Frequency Measurements
T.M. Winkel, L.S. Dutta, H. Grabinski, and E. Groteluschen,
University of Hanover, Germany

[5:35 - 5:40]
Fast Parameters Extraction of Multilayer and Multiconductor
Interconnects Using Geometry Independent Measured Equation of Invariance
Wei Hong, Weikai Sun, and Wayne Wei-Ming Dai,
University of California, Santa Cruz

[5:40 - 5:45]
An Optimum Pin Redistribution Algorithm for MultiChip Modules
Jun-Dong Cho, Sung Kyun Kwan University, Korea,
and Majid Sarrafzadeh, Northwestern University

[5:45 - 5:50]
Interconnect Delay Optimization Under Lossy Transmission Line
Tianxiong Xue, and Ernest S. Kuh, University of California, Berkeley,
and Qingjian Yu, Nanjing University of Science and Technology, China

[5:50 - 5:55]
Automation of the Advanced Interconnected Mesh Power System (IMPS)
MCM Topologies
James Patrick Parkerson and Leonard W. Schaper, University of Arkansas

[5:55 - 6:00]
Micro-Machined Heat Pipes in Silicon MCM Substrates
D. A. Benson, R. T. Mitchell, M. R. Tuck, D. R. Adkins, and D. W. Palmer,
Sandia National Laboratories, Albuquerque, NM

[6:00 - 7:00] Poster Display & Audience/Author Interaction
(Grand Ballroom)
Exhibits (Bay View Room)

[7:00 - 10:00] BANQUET

Wednesday, February 7, 1996

[7:30 - 8:30] Breakfast

[7:00 - 1:00] Registration

[8:30 - 9:45] SESSION VI: Electrical Design
Moderator: Thad Gabara, AT&T Bell Laboratories

[8:30 - 8:55] MCM-D Switching Units for Interconnection
Technology Validation
Claudio Truzzi, Eric Beyne and Edwin Ringoot, IMEC, Belgium

[8:55 - 9:20] Off-Chip 400MBPS Single-ended Signal Transmission
Using Non-resonant Lengths and Source-synchronous Clocking
Heinz Blennemann and Ron Nikel, Silicon Graphics Inc.

[9:20 - 9:45] A Functional Module Comparison of the Interconnected
Mesh Power System (IMPS) with a Standard Four-layer MCM Topology
Michael D. Glover and Leonard W. Schaper, University of Arkansas

[9:45 - 10:15] BREAK

[10:15 - 11:30] SESSION VII: Design Optimization
Moderator: P.R. Mukund, RIT

[10:15 - 10:40] Early Cost/Performance Cache Analysis of a Split
MCM-Based MicroSparc CPU
Peyman Dehkordi, Karthi Ramamurthi, and Donald Bouldin,
University of Tennessee

[10:40 - 11:05] Issues in Partitioning Integrated Circuits for
MCM-D/Flip-Chip Technology
Sanjeev Banerjia, Griff Bilbro, Alan Glaser, Chris Harvatis,
Steve Lipa, Real Pomerleau, Andrew Stanaski, Toby Schaffer, Yusuf Tekmen, and
Paul Franzon, North Carolina State University

[11:05 - 11:30] Chip and Package Co-design Technique
Qing Zhu and Wayne W.-M. Dai, University of California, Santa Cruz

[11:30 - 12:20] SESSION VIII: Computer-Aided Design
Moderator: Jason Cong, University of California, Los Angeles

[11:30 - 11:55] Early System Noise Analysis in Mixed-signal
Silicon-on-Silicon MCM Systems
Joe G. Xi and Wayne W.-M. Dai, University of California, Santa Cruz

[11:55 - 12:20] An MCM/IC Timing-Driven Placement Algorithm
Featuring Explicit Design Space Exploration
Henrik Esbensen and Ernest S. Kuh, University of California, Berkeley

[12:20 - 2:00] LUNCH


[2:00 - 3:15] SESSION IX: Advances in MCM Technology
Moderator: Paul Kohl, Georgia Tech

[2:00 - 2:25] Polymer Optical Couplers for Applications in
Multi-Chip Modules
Tsang-Der Ni and Dana Sturzebecher, US Army Research Laboratory

[2:25 - 2:50] New Type Structure Photo-Sensitive Polyimide
for High Density Wiring Multichip Module
K. Yokouchi, Y. Ishizuki, M. Yamamoto, D. Mizutani, and Y. Yoneda,
Fujitsu Laboratories Ltd, Japan

[2:50 - 3:15] New Olefinic Interlevel Dielectric Materials for
Multi-Chip Modules
R. Shick, B. Goodall, L. McIntosh, S. Jayaraman, P. Kohl,
S. Bidstrup-Allen and N. Grove, B.F. Goodrich Specialty Chemicals

[3:15 - 3:45] BREAK

[3:45 - 5:00] SESSION X: Modeling of Interconnect
Moderator: Steven Kang, University of Illinois

[3:45 - 4:10] An Accurate Determination of the Characteristic
Impedance of Lossy Lines on Chips Based on High Frequency S-Parameter
Thomas-Michael Winkel, Lohit Sagar Dutta and Hartmut Grabinski,
University of Hanover, Germany

[4:10 - 4:35] A New Moment Generation Technique for Interconnects
Characterized by Measured or Calculated S-parameters
M. Celik, A.C. Cangellaris, University of Arizona, and A. Deutsch, IBM

[4:35 - 5:00] Efficient Gate Delay Modeling for Large Interconnect Loads
Andrew Kahng and Sudhakar Muddu, University of California, Los Angeles

[9:00 - 5:00] EXHIBITS (Bay View Room)

Tutorials -- Monday, February 5, 1996

Tutorial #1 Known Good Die
8:30 -- 5:00 (Grand Ballroom)

Larry Gilg, MCC

This tutorial will cover the unique aspects of procuring and supplying
high quality bare die for advanced packaged electronic systems. A
thorough introduction to IC test and burn-in, and the issues that
most affect success in bare die use will lead into a discussion of
technologies available (or being developed) for fully conditioning
bare die. Emerging standards, including the all-important standards
being developed for die information will be covered. Cost implications
of differing test and burn-in strategies and technology will be
highlighted. A review of bare die available as Known Good Die, including
a description of the various levels of ``goodness" that die suppliers
are providing today will also be included.

Standards and Specifications
Known Good Die Assurance Technologies
Die Suppliers
Cost Analysis
MCM test strategies

Much of the material presented will be updated from last year's tutorial
with the progress in the KGD carrier evaluations and qualification activity
at MCC, updates from the SEMATECH low cost KGD project and information
from KGD and chip scale package activities in Europe and Asia.

Tutorial #2 Chip-Size Packaging Developments
8:30 -- Noon (Bay View Room)

Robert Crowley and Thomas Goodman,
TechSearch International, Inc.

Chip-size package (CSP) technology offers the assembly ease of surface
mount technology (SMT) with the small size and higher electrical
performance of flip chip technology. Chip-size packages are the same
size as the chip or generally no larger than 1.2 times the area of the
IC. In the last year, several companies have introduced new chip-size
packages targeting portable electronics applications. This tutorial
provides an overview of recent developments in this rapidly advancing
field of electronics packaging. The driving forces for CSPs are
discussed to explain the intense interest in this technology. The
alternatives to CSPs, such as ball grid array (BGA) and flip chip,
are analyzed. CSP technology from sixteen companies is presented and
compared. These technologies can be classified by interconnection
technique: flex circuit interposer, rigid substrate interposer, molded
structure, custom lead frame, wafer-level assembly, or TCP technology.
The barriers to CSP adoption are reviewed, including high-density PCB
availability, test socket availability, and contract manufacturer
availability. Tutorial participants will gain insight into the recent
worldwide developments in this field, as well as a better grasp of the
future impact of CSP technology on advanced packaging applications.

Tutorial #3 MCM-V (3-dimensional MCMs)
1:30 -- 5:00 p.m. (Bay View Room)

Peter Ivey and Jon Stern,
University of Sheffield, UK

Three-dimensional packaging can provide an order of magnitude reduction
in the volume and mass of a system. This is especially important in the
light of the dramatic growth in the portable electronics market. In this
tutorial a number of 3D MCM techniques will be presented and the merits
of each discussed. A detailed description, from applications to design
to manufacture, of MCM-V will be given. This versatile, low-cost,
epoxy-based 3D MCM that produces high density systems, while removing
the necessity for Known Good Die.

Registration Information

MCMC'96 will be held at the Cocoanut Grove in Santa Cruz, California
from Tuesday, February 6 to Wednesday, February 7, 1996.
A day of tutorials will be offered the preceding day, Monday,
February 5.

The conference registration fee of $295 for members*, $395 for
non-members, and $195 for students includes registration for the 2-day
conference, a copy of the conference proceedings, the Tuesday evening
banquet and two breakfasts and lunches. After January 26, the conference
registration fee is $365 for members, $495 for non-members and
$235 for students. (*Member = Member of IEEE or Japan Society of
Applied Physics (JSAP)).

There will be separate morning and afternoon tutorials on Monday,
February 5. Registrations will be accepted for individual or multiple
tutorials. Priority is given to conference registrants. Registration
for each half-day tutorial is $110 for members and $150 for non-members;
for the full-day tutorial the registration is $190 for members and $250
for non-members; there is no student rates for tutorials, per IEEE
Computer Society policy. Those registering for both a morning and
afternoon tutorial will receive lunch as well. After January 26, the
tutorial registration fee for each half-day is $135 for members and $185
for non-members; and full-day is $230 for members and $300 for non-members.

Refund Policy:
No refunds will be made unless written request for cancellation is
received prior to January 12, 1996. A $50.00 processing fee will be charged.

Phone Messages:
During the conference, messages for attendees may be left at the
Cocoanut Grove at (408)423-2053 and Fax (408)423-2438 between 9:00 a.m.
and 4:30 p.m.

Parking: Those staying at the Dream Inn will have free
parking at the hotel, and the Cocoanut Grove is a short walk
away. Those who will be commuting will need to park in the
parking lot across the street from the Cocoanut Grove. There
may be a parking charge after 10:00 a.m., but it will only apply
to those not already in the lot by that time.

The Cocoanut Grove, the Boardwalk, and Vicinity

The Cocoanut Grove is located on the beach, at the west end of the Santa
Cruz Beach Boardwalk, providing an elegance unequaled in coastal conference
facilities. Most of the meeting will be held in the Grand Ballroom,
with nearly 7,000 square feet of floor space. The MCM product and CAD tool
Exhibits will be shown in the Bay View Room outlined by a sweeping curve
of ocean view windows. Sunlight and blue skies, or moonlight and stars,
can be seen through the retractable glass ceiling of the Sun Room,
the location for the lunches and the Banquet.

Santa Cruz is a beautiful coastal town with many activities available
to visitors. You can, for example, deep sea fish, play tennis, skin dive,
surf, or play golf at internationally known courses. The Santa Cruz
Beach Boardwalk is the only remaining seaside amusement park in
California, open most weekends and holidays year round. Admission is free.

The weather in Santa Cruz in early February is generally cool and rainy,
with temperatures ranging from 37F to 59F (3C to 15C).
A warm sweater or jacket is recommended, particularly in the evening.

Conference Hotel

Blocks of rooms have been reserved for MCMC'96 at:

Dream Inn
175 West Cliff Drive
Santa Cruz, CA 95060
Refer to Group Number G2007
(408)426-4330 (For reservations only, call (800)421-6662.)
FAX (408)427-2025
$72 + tax for single or double rooms,

The Dream Inn is on the beach, near Cocoanut Grove and Fisherman's Wharf.
To get a room at the conference rates, you must register with the hotel
by January 18, 1996 and specify that you are attending MCMC'96.
Check-in time is 4:00 p.m., and check-out time is 12 noon.

Addresses and phone numbers of other hotels, motels, and
bed-and-breakfast places can be obtained from the
Santa Cruz Chamber of Commerce (408)423-1111 or the Conference and
Visitor's Council (408)425-1234.


United Airlines: MCMC registrants can take advantage of
United Airlines' agreement with the IEEE Electron Devices Society
to obtain a 10% discount (for Canada also) off the full coach fare,
or a 5% discount off any published fare for which the passenger may
qualify. You, your travel agent, or the person making your travel plans
can make reservations through the toll free UA Meeting Plus reservation
number 1-800-521-4041, available from 7 a.m. to 1 a.m. (E.S.T.),
7 days a week. Refer to the special EDS-MCMC96 code 587-NP.
Mileage credit will be received by all those who are members of
the UA Mileage Plus program. Reservations must be made at least 7 days
prior to departure.

Airports: The closest airport is San Jose International, about
45-60 minute drive away (except during rush hours). San Francisco
International Airport is 1-1/2 to 2 hours away. Peerless Stages
operates a bus four times a day between the San Jose airport and
downtown Santa Cruz, costing $8.00 and taking about an hour and a quarter.
Call them for more information at (408)423-1800.

Both San Francisco and San Jose airports are served by various van
services: the Santa Cruz Airporter (408)423-1214 or (800)497-4997 has
service every two hours, reservations recommended;
ABC Transportation (408)464-8993 or (800)734-4313 (CA only) requires
reservations. Call them directly for prices and travel times.

Those driving into Santa Cruz should take Highway 17 South.
Continue north on Highway 1 (Mission Street) and turn left on Bay
Street for the Dream Inn and Cocoanut Grove.

For conference information contact:

Lisa Pascal -- MCMC-96
[email protected]
Computer Engineering
University of California
Santa Cruz , CA 95064