RE: [SI-LIST] : micro BGA SI vrs PCB consideration

Dave Hoover ([email protected])
Thu, 14 Oct 1999 11:37:16 -0700

It sounds like Ron's mentioning a process called sequential lam
where a portion of the PCB is drilled and plated, then relaminated where
the PTH's fill with resin. Then the excess resin is removed and final copper
plate is rendered over the top. That's another option for via-in-pad.

-----Original Message-----
From: Ron Miller [mailto:[email protected]]
Sent: Thursday, October 14, 1999 11:07 AM
To: [email protected]
Subject: Re: [SI-LIST] : micro BGA SI vrs PCB consideration


I have successfully used via-in-pad for high performance loadboards with
no problem. The technique to eliminate the solderwicking that we used was
to fill the holes with epoxy, clean off surface epoxy and finally plate the
surface for
pads. Hadco in Santa Clara did this for me, and it worked fine.

Ron Miller

Matt Kaufmann wrote:

Be careful when you talk about via-in-pad. Yes, a microvia is technically a

via-in-pad and would be acceptable (and probably advisable for fine pitch
parts (<1 mm)) but via-in-pad can also denote a drilled via in the center of

the BGA pad which is a big no-no since the via can wick solder away from the

joint (a microvia will not have this problem since the via is terminated at
the second layer).


Matt Kaufmann
Senior Packaging Engineer
Silicon Spice Inc.
415 East Middlefield Road
Mountain View, CA 94043-4005
408-806-9680 (cell/pager)
650-940-7770 (fax)
[email protected]

> -----Original Message-----
> From: [email protected]
> [ mailto:[email protected]
<mailto:[email protected]> ]On Behalf Of Dave Hoover
> Sent: Thursday, October 14, 1999 8:22 AM
> To: '[email protected]'
> Subject: RE: [SI-LIST] : micro BGA SI vrs PCB consideration
> You can use that stack-up from a PCB fab standpoint.
> The microvias can go to layer 2 (or layer 3 or 4).
> The real issue is the following:
> 1) The microvia needs to be <=.7:1 Aspect Ratio.
> This is to guarantee the plated hole quality. (+/- 3 sigma)
> 2) The depth of the microvia needs to be evaluated from an
> assembly approach. For example, for via-in-pad will
> the microvia create a huge bubble during reflow? If so
> does the solder void violate the 20% max rule?
> I agree that for CSP (<.8mm pitch grid array packages) that
> microvia is the best approach. It allows more rout channels
> for signals.
> You can have signals on the outerlayers also. Via-in-pad
> provides more room for that. You can even have a plane
> on layer 2 with a signal on 3 to have the plane act as an
> EMI shield. (Get noisy clocks under a plane) like...
> sig (c/s)
> pln
> sig
> ...
> There are MANY reasons I've seen for MicroVias. Here's just
> a few.
> 1) Fine Pitch BGA. (Like CSP, FPBGA, DSP. Pitch's less that 1.0mm)
> 2) Via-in-pad. (To free up real estate under the BGA's so termination
> resistors and caps can be mounted as close as possible to the device)
> 3) Dropping a noisy clock/signal below a plane (to lyr 3) for EMI/EMC
> reasons.
> 4) Providing distributed plane capacitance right at the solder ball
> (no lead inductance which can degrade electrical performance on
> high speed devices)
> 5) Separating Logic types on the PCB on one side only with something
> else on the other. With microvias you could leave the planes intact
> with no clearances or "swiss cheese" effect.
> (i.e., Analog, Digital, RF, Control, or Microwave)
> 6) Connecting directly to planes for heat dissipation (or pwr)
> without "swiss cheesing" the plane(s).
> That's just a few. It looks like when the PCB (or substrate) get's
> greater than 130 Holes per square inch, then microvias (or
> buried/blind vias) are necessary.
> Common PCB types using microvia are:
> Portable Consumer Products
> like GPS, PDA, camcorders, PCS, and Cellular Phones.
> Interposer/Adapter Boards
> like BGA to CSP, QFP to BGA, CSP to BGA (The skys the limit here)
> Organic Chip Carrier Packages (FlipChip, PBGA, MCM-L)
> like CSP or microBGA
> Wireless Products
> like Wireless Base stations
> Memory Modules
> like SIMM
> Computer Networking Cards
> like PCI, Compact PCI, Mother Boards
> What have I forgot?
> Dave
> -----Original Message-----
> From: Ilan Adar [ mailto:[email protected]
<mailto:[email protected]> ]
> Sent: Thursday, October 14, 1999 5:02 AM
> To: [email protected]
> Subject: [SI-LIST] : micro BGA SI vrs PCB consideration
> hallo
> We run into some problems when using micro BGA.
> We used PTH vias between the micro BGA pads and this leads us to
> low yield in the manufacturing .
> the PCB people tell us that we must use micro via technology, but this
> requires us
> to change the PCB stack to :
> CS
> ..
> ..
> ..
> ..
> can I use such a stackup ? or is there a mother solution to micro BGA PCB
> layout.
> thanks very much
> Ilan Adar
> [email protected] < mailto:[email protected]
<mailto:[email protected]> >
> tel 972-9-7751239
> Fax 972-9-7751212
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Ronald B. Miller _\\|//_ Signal Integrity Engineer

(408)487-8017 (' 0-0 ') fax(408)487-8017


Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA 95131

[email protected], [email protected]

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