> If this simulation includes the in-situ parasitics the edges are right where
> they should be. I use these parts and can tell you that's what they do. I
> wouldn't suspect the model. As far as not reaching Vdd, all I can say is that's
> not desireable, whatever the cause. You did not describe the circuit topology:
> is it simply point_to_point Xilinx to single memory chip?
>
Yes, it is point to point between the Xilinx and the ZBT and there are two
terminating resistors, one near the FPGA pin and one near the ZBT pin of
course. Even though the terminations are not strictly necessary to eliminate
reflections (the traces are at most 2 inches long), from the simulations I
see that the integrity of the signals improves a lot when I include them, and
I believe that this is due to the damping of the RLC circuit that we have
when we consider the pin parasitics.
-Arrigo
-- Dr. Arrigo Benedetti e-mail: [email protected] Caltech, MS 136-93 phone: (626) 395-3695 Pasadena, CA 91125 fax: (626) 795-8649**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****