We are designing some high-density digital boards with clock frequencies
of 40 and 50 MHz. Our general policy (virtues of which are for another
discussion) is to create a separate filtered power supply area for each
block of logic, using 3-terminal EMI power filters. As a result, each
power plane is carved up into a bunch of local islands, fed by either
a common "trunk" on that plane, or from a redundant, solid plane (the
latter is a possibility we haven't explored too deeply yet.)
The most immediate consequence of this is that the power plane is no longer
a return path for signals that cross the cuts, which leads to the question:
What is the effect of having a signal sandwiched between a continuous
ground plane and a carved-up power plane? How do we model the impedance?
It would seem that signals which don't cross the cuts are standard
striplines, whereas for those which do cross the cuts, the plane is not
considered a plane anymore.
Clearly, we would not use these oddball layers for controlled-impedance
critical signals, but how bad would they be for high-speed non-criticals?
A sample 10 layer stackup would look like this:
1 S
2 Ground (continuous)
3 S
4 Power (carved)
5 S
6 S
7 Power (carved)
8 S
9 Ground (continuous)
10 S
Layers 5 and 6, sandwiched between two carved up power planes, are
restricted to routes which do not cross any plane cuts.
Layers 3 and 8 are the more interesting ones in question.
Any useful references would also be appreciated.
Thanks,
- Neil
------------------------------------------------
Neil Weinstock ViaGate Technologies
[email protected]
- Neil
------------------------------------------------
Neil Weinstock ViaGate Technologies
[email protected] (908) 595-6400 x4525
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