RE: [SI-LIST] : Decoupling strategy in tight spaces

Greim, Michael ([email protected])
Wed, 15 Sep 1999 08:54:59 -0400

Chris et al,

You don't give alot of information regarding system frequency,
current requirements or edge transitions but I can give my two cents
worth if it will help.

First, I'm not exactly following you regarding component selection.
You should be able to get larger capacitance values than 4700 pf
in an 0805 package from any number of different vendors. In a
worst case scenario you can always turn to Digikey as a starting
point. Are you limited to existing stock as your choice? Is there
a wattage issue that hasn't been illuminated? If these aren't a
factor than you should be able to find 0603 components to fit
your need and real estate.

Second, If you are concerned about inductance, you might want
to consider a reverse form factor capacitor. What this is (for those
who don't know), is a smt cap that has the contact on the long side
of the device. As you might expect, they are called out by vendors
for example as an 0508 cap, as opposed to the other way around.
AVX and Vitramon support this as well as others. Note: there may
be an issue with lead times on these.

Third, recognize the difference between decoupling the part and
decoupling the plane. Getting a capacitor close to a power pin
is a good start but not as good as a direct connect to the part.
with a standard config, a power pin on a device will use a via
to get to the power plane and then another to get back up to
the capacitor. A preferable method would be to go directly from
the pad of the device to the pad of the cap, and THEN through
a via down to the plane. This will significantly cut down on the
inductance of your scheme. Again, look at your via structure to
the plane may also help. Your power vias may have a different
topology than your signal vias.

Fourth, Make sure that you have enough capacitance. With
today's new power hungry, multi-MHz chips, one cap per pin
or one via per cap, might not be enough. At least go through
a first pass approx with I = C dV/dt and see where you sit.
Drooping power planes are a bad thing and can be pretty
easily avoided if paid attention to.

Fifth: Your multi-capacitor approach is good. I would
still check my values as we just got through a COTS/ROTS/MOTS
program and there is a BIG difference between mil-spec and
MIL temp. In fact, most programs have gone over to I-temp
requirements, so I'd check on that.

Six: Don't Ignore Bulk decoupling. A few quick checks should
convince you that you have what you need.

Hopefully this helps you out.

Best Regards,

Michael C. Greim Consulting Engineer
Mercury Computer Systems, Inc email: [email protected]
199 Riverneck Road V:
Chelmsford, MA 01824-2820 F: 978-256-4778

> -----Original Message-----
> From: Chris Bobek [SMTP:[email protected]]
> Sent: Tuesday, September 14, 1999 9:19 PM
> To: Si-list
> Subject: [SI-LIST] : Decoupling strategy in tight spaces
> Hi,
> I am trying to come up with a decoupling strategy for a board I'm
> working on. Unfortunately, there are some constraints that make it more
> difficult than other boards I've done.
> For various reasons (i.e., mil project), we have the following
> capacitors to work with:
> 4700pF -- 0805 (largest value for smallest case size, for our
> application)
> 0.1uF -- 1812 ("")
> 15uF -- 0.6ohm ESR, 1412
> For parts with a lot of switching and I/O, my thoughts were to:
> - use a 4700pF at each power pin because it has a smaller case size than
> the 0.1uF which will yield lower inductance, thus better response for
> higher freq's.
> - use a 0.1uF at each power pin for most of the other freq's.
> - use the low ESR 15uF where possible to provide large switching
> currents
> For other, smaller parts, I would just use a mix of 4700's and 0.1's.
> Are there any major problems with my reasoning? Does anybody have
> "better" recommendations... and can back them up ;-)
> I will follow this question up with another later, concerning capacitor
> placement and vias.
> Thank you,
> Chris
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