Refer to the input impedance measurements in a separate message posting
done on 74AHCT245 and 74ACTQ245. These are bidirectional inputs. These
measurements were done with an HP impedance analyzer. The devices were in
SO20 packages.
A few comments on interpreting the plots. The marker is at 40MHz and the
equivalent series capacitance and resistance is shown at the upper right
hand corner of the plot. The measurements lose accuracy at very low
frequencies since the impedances get very large (capacitive reactance). At
the top of each plot the top and bottom (T&B) indicate the limits of the
plot, 0 to 20 ohms, 0 to 10pF. These measurements were done at an input
voltage bias of 0volts. The frequency range is from 100kHz to 300MHz. The
DC bias conditions are noted on the plots at 0 volts and 0 mA input current.
Other custom I/O cells I've measured have very different characteristics.
Some change substantially with input DC bias.
So this leaves us with the question of what causes excessive ringing in
simulations. The enclosed measurements show high Q capacitive inputs--the
ringing in simulations must be caused by something else. The bond wires
should be quite high Q inductors, and the inputs (at least some types of
bidirectional inputs) are also high Q capacitors. The bond wire length is
very much shorter than a wavelength at the ringing frequency so a
distributed parameter model (rlgc) shouldn't be necessary. The mutual
coupling in the package could affect the ringing, and the ESR of the power
to ground (which should be high) might also.
Another possibility is the models for the transmission lines which are
connected to the IC inputs are simply not valid over the entire frequency
range--sections of cascaded RLGC sections are only valid over a limited
frequency range, one needs to increase the number of sections to increase
the frequency range. Or perhaps the increasing loss with frequency seen in
PCB and cables dampens the ringing at higher frequencies.
Any explanations/thoughts?
Chuck Hill, consultant
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