All,
Todd ment to say:
"Everything with Len=0 is a lumped value, while everything with a nonzero
Len is actually being modeled as a transmission line."
Regards,
scott
Todd Westerhoff wrote:
> Everything with L=0 is a lumped value, while everything with a nonzero L is
> actually being modeled as a lossless transmission line.
> .
>
> At 12:41 PM 9/8/1999 -0700, you wrote:
> >I face the following puzzle in running a signal integrity
> >simulation on Pentium II board. I'm using SpecctraQuest
> >and Signoise, in case this matters.
> >
> >I have a Pentium II IBIS model (which I converted to Cadence's
> >.dml format). This model appears to model all the parasitics
> >of the Slot 1 board in a lumped manner; I presume that the
> >model includes parasitics up to the edge fingers. (Does anyone
> >know different?)
> >
> >I also have a model of a Slot 1 connector in SPICE format. Quite
> >aside from issues of how this model is to be used (I'm trying to
> >get the answer to that from the supplier) is the issue of how to
> >include the Slot 1 connector parasitics in the simulation. At
> >first, I thought I could use a design link and treat the connector
> >as a cable connecting the main board and the Slot 1 module, but I
> >think that requires that I have the "board layout" of the Pentium
> >module. The next thought was to treat the connector as a package, but
> >this doesn't work since the Pentium II module is already a package
> >model. So I'm left with adding the connector parasitics in some
> >fashion to the existing Pentium II model. I just want to check
> >that this is in fact the correct approach, or else find out whether
> >I'm giving up too soon on one of the first two approaches mentioned,
> >or whether there's another approach I haven't considered.
> >
> >I'm sure I'm not the only one facing this, so how are others
> >solving it?
> >
> >
> >--
> >Kim Helliwell
> >Senior CAE Engineer
> >Acuson Corporation
> >Phone: 650 694 5030 FAX: 650 943 7260
> >
> >**** To unsubscribe from si-list: send e-mail to
> [email protected]. In the BODY of message put: UNSUBSCRIBE
> si-list, for more help, put HELP. si-list archives are accessible at
> http://www.qsl.net/wb6tpu/si-list ****
> >
> >
> >
>
> Todd Westerhoff
> Technical Marketing Director | High Speed Systems Design | Performance
> Engineering
> Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824
>
> ph: (978) 262-6327
> fx: (978) 446-6798
> email: [email protected]
> internal information website: http://www-ma.cadence.com/~toddw
>
> **** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
-- Scott McMorrow Principal Engineer SiQual, Signal Quality Engineering 18735 SW Boones Ferry Road Tualatin, OR 97062-3090 (503) 885-1231 http://www.siqual.com
--------------C05A0FBA42822A525B528965 Content-Type: text/x-vcard; charset=us-ascii; name="scott.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Scott McMorrow Content-Disposition: attachment; filename="scott.vcf"
begin:vcard n:McMorrow;Scott tel;work:503-708-4320 x-mozilla-html:FALSE url:www.siqual.com org:SiQual, Signal Quality Engineering adr:;;18735 SW Boones Ferry Road;Tualatin ;OR;97062-3090;USA version:2.1 email;internet:[email protected] title:Principal Engineer note:asdfsdaf fn:Scott McMorrow end:vcard
--------------C05A0FBA42822A525B528965--
**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****