Sorry for the delay in reply.
Actually, the Intel processor cartridge models have typically included the
parasitics for the connector as part of the catridge model. The reasoning
is simple; there's no point in modeling/simulating the cartridge by itself,
since it never gets used that way.
The cartidge parasitics are also normally not lumped, but include a
collection of transmission line statements in addition to lumped parasitics
for things like pad and pin capacitance ... careful inspection of the .EBD
file will tell you which is which:
(from developer.intel.com)
|PROC_I_GTL_FAST_PAK | PROCESSOR GTL "FAST" CARTRIDGE MODEL
[Path Description] B31
Pin B31
Node SC242.B31 | PIN OF SC242
Len = 0.66 L = 1.33333e-08 C = 2.08333e-12 / | SC242 CONNECTOR
Len = 1.500 L = 1e-08 C = 1.77778e-12 / | PROCESSOR SUBSTRATE TRACE
Fork
Len = 0.900 L = 1e-08 C = 1.77778e-12 / | TRACE TO TERMINATION RESISTOR
Node RTT56.B31 | GTL PULL-UP RESISTOR
Endfork
Node PIN.B31 | CORE PKG PIN
Len = 0 L = 0.91E-9 / | CORE PAD INDUCTANCE
Fork
Len = 0.02 L = 1.76183e-08 C = 1.90773e-12 / | TIE BAR
Endfork
Len = 0.15 L = 1.034e-08 C = 3.25059e-12 / | PKG TRACE - STRIPLINE
Len = 0.08 L = 1.68483e-08 C = 1.99492e-12 / | PKG TRACE - MICROSTRIP
Len = 0 R = 0.125 L = 1.93E-9 / | BOND WIRE RESISTANCE & INDUCTANCE
Node PAD.B31 | CORE PAD
Everything with L=0 is a lumped value, while everything with a nonzero L is
actually being modeled as a lossless transmission line.
Intel was nice enough to comment a lot of this stuff, so you can wade
through the package parasitic and figure out what is being used to model what.
So, the point is, you shouldn't need to model the connector separately,
because it's being modeled as a 0.66" piece of Tline (from the above
syntax) with a specific inductance and capacitance per unit length.
Hope this helps,
Todd.
At 12:41 PM 9/8/1999 -0700, you wrote:
>I face the following puzzle in running a signal integrity
>simulation on Pentium II board. I'm using SpecctraQuest
>and Signoise, in case this matters.
>
>I have a Pentium II IBIS model (which I converted to Cadence's
>.dml format). This model appears to model all the parasitics
>of the Slot 1 board in a lumped manner; I presume that the
>model includes parasitics up to the edge fingers. (Does anyone
>know different?)
>
>I also have a model of a Slot 1 connector in SPICE format. Quite
>aside from issues of how this model is to be used (I'm trying to
>get the answer to that from the supplier) is the issue of how to
>include the Slot 1 connector parasitics in the simulation. At
>first, I thought I could use a design link and treat the connector
>as a cable connecting the main board and the Slot 1 module, but I
>think that requires that I have the "board layout" of the Pentium
>module. The next thought was to treat the connector as a package, but
>this doesn't work since the Pentium II module is already a package
>model. So I'm left with adding the connector parasitics in some
>fashion to the existing Pentium II model. I just want to check
>that this is in fact the correct approach, or else find out whether
>I'm giving up too soon on one of the first two approaches mentioned,
>or whether there's another approach I haven't considered.
>
>I'm sure I'm not the only one facing this, so how are others
>solving it?
>
>
>--
>Kim Helliwell
>Senior CAE Engineer
>Acuson Corporation
>Phone: 650 694 5030 FAX: 650 943 7260
>
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>
>
>
Todd Westerhoff
Technical Marketing Director | High Speed Systems Design | Performance
Engineering
Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824
ph: (978) 262-6327
fx: (978) 446-6798
email: [email protected]
internal information website: http://www-ma.cadence.com/~toddw
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