RE: [SI-LIST] : FR-4 and PCB Tolerances

Abe Riazi ([email protected])
Sun, 29 Aug 1999 20:42:15 -0700

Hi Dave:

Thanks for your posting and several other recent emails which
offered fresh insight related to FR-4 variations. I am very interested
in manufacturing tolerances for various FR-4 characteristics (including
losses, thickness and dielectric constant) at high frequencies
particularly the 33 MHz to 400 MHz range. As stated in previous
communications, SI simulations are often performed for three corners:
Maximum, Nominal and Minimum. These simulation corners are also
referred to as Fast, Typical and Slow. As mentioned in my earlier
email (that you had referred to), one set of values recommended for FR-4
dielectric constant are 4.2, 4.4, and 4.6 for fast, typ and slow corners
respectively. It is possible for this Er' variation to cover a wider
or narrower range (depending on several factors such as frequency,
application and capabilities of PCB manufacturer). I have not seen the
"military specs" for allowed tolerances of FR-4 attributes, but it would
be interesting to know how tight are such military tolerances (of
course, if they are not classified material).


Abe Riazi
[email protected]

>From: Dave Hoover[SMTP:[email protected]]
>Sent: Friday, August 27, 1999 10:23 AM
>To: [email protected]
>Subject: [SI-LIST] : FR-4 and PCB Tolerances
>Patrick wrote:
>I always pay a close attention to effects of manufacturing tolerance
>variations. SI simulations are carried out for three corners (i.e.
>fast, typ and slow), and numerous model and PCB parameters are allowed
>to vary according to tolerance requirements. For instance, the value of
>substrate dielectric constant may be 4.2 for fast, 4.4 for typical and
>4.6 for slow corners. Similarly, substrate thickness for fast, typical
>and slow corners can be 5.2 mils, 4.5 mils, and 3.8 mils respectively.
>This is considered necessary to verify the design under all conditions.
> Experience has proven to me that "stackup extraction", which I had
>attempted to explain clearly in my communication, is important. It can
>serve to eliminate numerous SI simulation problems and enhance
>simulation accuracy.
>Here's my 2 cents on FR-4 variation. See the attached file.
>The Er' is a result of the resin to glass ratio. The thinner B-Stage
>prepreg has a higher resin content which results with a lower Er'.
>However, it would not be in best interests to try and build an .062"
>thk PCB out of .002" thick prepregs. Yes, the Er' would be low but the
>would be through the roof along with the resin flow out of the
>press. The dimensional (in)stability could produce misregistered layers.
>(Too much movement) As a fabricator, we use the various prepreg styles
>to satisfy many things. (Some are.....)
>1) To achieve the desired dielectric thickness. (i.e., the thicker plies
> may achieve the best cost approach but possibly not supply
> sufficient resin to displace the air during pressing. So we would use
> two plies rather than single ply.)
>2) Meet overall thickness.
>3) Meet desired electrical performance requirements. (i.e., Zo, Zdiff,
> L, C, Co, Tpd)
> FR-4 is (as you know) lossy. So when FR-4 is used at higher
>frequencies (e.g. >500 MHz) there is some substantial differences than
>the published technical data sheets from the material suppliers that
>tested the substrates @ 1 MHz. TDR has a nominal BW at around 1 GHz
>(based on FR-4 along with 6" long TDR Coupons) so we (fabricators)
>see most modeling programs matching "modeled vs. actual" data with a
>Er' at around 10% lower than what's published. (i.e., 4.4 vs. 4.0 Er')
> The successful fabricators develop PCB attributes that yield
>desired results. These PCB attributes are recorded and stored for future
>reference (Empirical data). Sometimes, there is many different ways
>to achieve a desired dielectric thickness. Each (prepreg) combination
>requires a slightly different linewidth to achieve desired Zo
>(due to subtle Er' differences). This includes prepreg resin fill
>yield and Er' characteristics from the designed circuitry off the
>various innerlayer.
>So Pat's comment of:
> "I always pay a close attention to effects of manufacturing tolerance
>variations.".... is better understood.
>The art of PCB manufacturing (as previously stated) definitely
>is not an exacting science. However, by monitoring and tracking
>the variations encountered with building the PCB, the required
>PCB attributes along with the tolerances can be anticipated.
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