I appreciate the feedback that you and others have provided me, and
apologize that a busy schedule prevented me from responding earlier.
After reading your email and also comments of Pat Zabinski and
Patrick Riffault, I feel that there is some misunderstanding as to what
"stackup extraction" can and can not accomplish. Perhaps the following
explanation can help to clarify the limitations and capabilities of this
methodology.
Stackup extraction can not be used to obtain details regarding
parasitics, mutual coupling, manufacturing tolerances, device class,
etc. However, it can gain information related to the number of layers
, type (i.e. plane or signal), and exact name (example: TOP, INNER3,
GND5, VDD, etc.). It can be also utilized to determine at which layers
the pads and traces are located and thereby examine connectivity.
Stackup extraction by itself does not furnish all of the necessary
stackup details. I utilize the information extracted to check and to
supplement stackup diagrams frequently prepared by the circuit or PCB
designers. This allows inputting the most accurate stackup to the
simulator (for example accurately creating for complex boards the
stackup section of QUAD's Global Control File .GCF). Stackup extraction
can also serve as a powerful diagnostic tool.
I have extracted numerous ALLEGRO and PADS-power PCB databases.
They all have yielded useful stackup information. I have found ALLEGRO
databases to be more convenient, for purpose of extraction and SI
simulations, than PADS databases.
Regards,
>----------
>From: Todd Westerhoff[SMTP:[email protected]]
>Sent: Monday, August 16, 1999 2:25 PM
>To: [email protected]
>Subject: Re: [SI-LIST] : Stackup Extraction
>
>(...)
>
>>
>> I. ALLEGRO DATABASES
>>
>> An ALLEGRO PCB database (i.e. a .brd file) can be viewed by an
>>Allegro viewer program, freely available from the Cadence Web Site,
>>which identifies and displays the stackup of the design. For example
>>stackup of an eight layer board (consisting of four signal layers, three
>>ground, and one power layer) using Allegro viewer, is identitfied as:
>>
>> TOP
>> GND2
>> INNER3
>> VDD
>> GND5
>> INNER6
>> GND7
>> BOTTOM
>>
>> When extracting an Allegro database, I also examine the Layer.dat
>>file ( an ASCII data file which results from the .brd file after
>>execution of the Allegro EXTRACT utility batch program) for stackup
>>details. For example, the following section of a Layer.dat file includes
>>information regarding the thickness and dielectric constant of the Top
>>layer, ground layer, an inner signal layer and substrate:
>>
>> S!1!TOP!POSTIVE!!YES!!595900mho/cm!COPPER!NO!3.98 w/cm-degC!1.2mil!
>> S!2!!!NO!4.500000000000e+000!0 mho/cm!FR-4!!0.012 w/cm-degC! 8mil!
>> S!3!GND2!NEGATIVE!EMBEDED_PLANE!YES!!595900 mho/cm!COPPER!YES!3.98
>>w/cm-
>> degC!1.2mil!
>> S!4!!!!NO!4.500000000000e+000!0 mho/cm!FR-4!!0.012 w/cm-degC!8 mil!
>> S!5!INNER3!POSITIVE!!YES!!595900 mho/cm!COPPER!NO!3.98 w/cm-degC!1.2
>>mil!
>
>(...)
>
>Abe,
>
>As you point out, the Allegro database "cross sectional characteristics"
>contain data for layer thickness, dielectric constant and conductivity.
>That information, combined wi the trace information, allows post-layout
>circuit equivalents to be accurately extracted.
>
>Allegro database information such as cross sectional characteristics,
>device CLASS, PINUSE, etc. is often not set up correctly in a given
>database. Layers have certain default properties unless overridden with
>actual values by the user. Since the electrical information is not
>actually needed to manufacture the board, some people never set this up in
>the database.
>
>Bottom line, you need to make sure the electrical characteristics specified
>in the Allegro database are correct for the board under consideration, or
>your SI analyses are for naught. Some SI tools that rely on data extracted
>from .dat files (as you mention) allow the board's cross sectional
>characterisitics to be specified in a separate text file - but this is
>really a poor second to putting the correct data in the Allegro database to
>begin with.
>
>Todd.
>
>
>
>
> Todd Westerhoff
> Technical Marketing Director | High Speed Systems Design | Performance
>Engineering
> Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824
>
> ph: (978) 262-6327
> fx: (978) 446-6798
> email: [email protected]
> internal information website: http://www-ma.cadence.com/~toddw
>
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