Re: [SI-LIST] : Stackup Extraction

Pat Zabinski ([email protected])
Mon, 16 Aug 1999 07:56:47 -0500

I'd like to take this a few steps further:

#1 - As has been discussed in this list before, PCB manufacturing
is not an exact science, and you are not likely to know the cross
section until after it has been fabricated. PCB vendors must "tune"
the cross section during fab to obtain the customer's desired
characteristics (overall board thickness, 50 ohm lines, etc.), and
cross section is generally one of "tuned" parameters. (pretty
much in-line with Patrick's comments below)

#2 - I've been using Allegro for eight years for everything from
single chip packages to MCMs to large PCBs, and I have rarely
entered the material parameters into the tool. Although Allegro
does have an integral tool that spits out some basic parasitics
for lines (Z0, C, L, Td, etc.), I have never relied on it. The
only time I've ever entered in the material parameters/thicknesses
is for documentation purposes. Because it is not necessary
to enter in the cross section (i.e., it's an extra unnecessary
step), I'll venture a guess that many other designers avoid
entering it as well.

#3 - Several parameters that influence SI are not available in
the cross section data, including dielectric loss tangent, surface
roughness, mesh plane geometries, etc.

In all, I agree with Patrick's comments "... I would not rely
on the extracted information to determine if a board passes SI."

Pat Zabinski

> Abe
> Although obtaining an accurate representation of a stackup is
> necessary when doing simulations I would not rely on the
> extracted information to determine if a board passes SI.
> I would use the ranges that were specified when the PCB
> was designed to ensure that everything will work over all manufacturing
> ranges (example dielectric of 4.1 to 4.7, trace width of
> 4.8 to 5.2 mils). The extracted information is only one of many
> combinations permitted by the design.
> Regards,
> Patrick

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