In picking a driver, you have a lot of factors to consider concurrently:
1) Input-to-output delay relative to your clock cycle time.
2) Output impedance relative to transmission line impedance and loading.
3) Rise/fall time - not too fast and not too slow. 10-20% of the clock cycle is
a good place to start
4) Capacitance.
5) di/dt for simultaneously switching output (SSO) noise.
For items 1-4, you should be able to make your decisions based on a single-net
analysis using the loading you expect your driver to see. When you do the di/dt
simulations to determine signal-to-return ratio and worst-case SSO noise, you
will need an accurate coupled model for the package. I like to start with
empirical calculations to get a feel for the problem and then use a field solver
to derive an accurate package model.
Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
[email protected]
---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on 07/23/99
10:36 AM ---------------------------
chenlanbing <[email protected]> on 07/21/99 01:53:33 AM
Please respond to [email protected]
To: [email protected]
cc:
Subject: Re: [SI-LIST] : How to treat the ASIC package pin-assigns
Hi!
Thanks for your help.It is very important in ASIC package design.I think it is
the same as the connector pin assigns in SI.If you have no good pin assigns in
high-speed ASIC package,maybe it can't work.Mr Pratapneni suggest we
might have to simulate the effective improvement by field solvers and SI
tools.Can you tell me which tools should be used and the ways to design the
package including choosing package and the pin assigns.I'm newman in the package
design.Wish get your help.
In the same time,the ASIC buffer choice is important too.Can anyone tell me how
to simulation the ASIC buffer in the future applied conditions and get a good
buffer to improve the ASIC's SI.
Chenlanbing
[email protected] wrote:
> Hi! Chenlanbing,
>
> It depends broadly on following things:
>
> (a) what kind of package: ground return path within the package is different
>
> for different types of packages (stack-up of the package dictates this). In
> BGA type packages
> there are usually metal islands for gnd and pwr(connected to their
> respective power/ground planes thorough vias), you can isolate other noises
> by
> assigning a separate island to clock power/ground (if you have such a case)
>
> In the past I have assigned two dedicated pads for power and ground around
> the
> clock pad within AISC.
>
> Also it is helpful to put quiet buffers around a clock pad. This is also
> dependent upon the fact how your power distribution is with the chip.
>
> (b) Clock type (is it differential), noise sensitivity, drive strength etc:
>
> If clock net is very noise sensitive then you can provide noise isolation at
> package level by customizing the power/ground planes. But you might have to
> simulate the
> effective improvement by field solvers and SI tools.
>
> you can isolate power/ground distribution at chip level as well if you have
> that freedom.
>
> -Satish Pratapneni
> Signal Integrity Engineer
> Dell Computers Corporation, TX
> (512)723-8436
>
> -----Original Message-----
> From: chenlanbing [mailto:[email protected]]
> Sent: Saturday, July 17, 1999 4:54 AM
> To: [email protected]
> Subject: [SI-LIST] : How to treat the ASIC package pin-assigns
>
> Hi,
>
> Now I have a ASIC package design.There is a lot of data bus and a clock
> signal in this package.
> How can I do the pin assigns?If I put the clock pin beside the data pins and
> insert a gnd pin,can it improve the SI?
> I need your helps and wish can get some advices about how to pin assign the
> ASIC package.I know it is very key in HSSD to pin assign the connector and I
> can get a good pin assign by simulation.
>
> Sincerely,
>
> Chenlanbing
>
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