chenlanbing ([email protected])
Wed, 21 Jul 1999 19:12:43 +0800


This question is very interesting.According to my experience,it is no problem
if the overshoot time is much less than the pulse time.But I don't know how
much the minimum ratio of the overshoot time to the pule time is.Can anybody
answer this question?




> We find that that with the sub nano second edges on today's drivers,
> almost every unterminated signal has an overshoot that exceeds the
> maximum voltage rating on the input, if it is more than 1inch away from
> the output.
> As an example, I am driving with a 500ps edge into a SAMSUNG Memory
> KM736V887. The SSRAM is 2 inch away from the driving chip, and my
> simulation result shows an overshoot of 4.2V in a point-to-point
> topology. Samsung specifies a 'absolute maximum voltage' for this input
> of 3.6V.
> Would you put a series termination on this net?
> Those maximum voltage specs, we find in the data sheets consider a DC
> voltage, but what would be the AC margin for this parameter. Of course
> it is higher - but how high? Could I consider 2 times the DC maximum
> voltage rating for transients as a safe and simple design rule?
> I guess the question is, does anybody care about overshoot on
> data/address busses before the actual sampling time? If yes, what would
> you consider to be an acceptable overshoot?
> Our products have to meet long term reliability requirements and I would
> think latch up can not be the only failure mechanism to consider.
> Any comments would be greatly appreciated
> Joachim
> ------------------------------------------------------------------------
> Joachim Mueller <[email protected]>
> EMC-Engineer
> Newbridge Networks Corporation
> Joachim Mueller
> EMC-Engineer <[email protected]>
> Newbridge Networks Corporation
> 600 March Road Work: 613-591 3600
> Ottawa Fax: 613-599 3654
> Ontario Netscape Conference Address
> K2K 2E6 Netscape Conference DLS Server
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> Additional Information:
> Last Name Mueller
> First Name Joachim
> Version 2.1

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