This assumes, of course, that there is really
a true differential receiver used, not just a pair of=20
complementary single ended inputs.=20
With the difficulty of keeping the true and false side of=20
a differential signal balanced *very* precisely from the
source through interconnect, packages, die connections, and
even across the die, it can be really difficult to not=20
introduce a few tens of picoseconds of phase offset. What
does that do to the CMRR versus frequency? Probably still
pretty good at low frequency, but how about the frequencies
of the harmonics of the fast edges? Will use of differential
signals produce any real advantages at those frequencies?
Jerry Johnson
VLSI Test Division
Teradyne
> Date: Mon, 19 Jul 1999 11:04:03 -0700
> From: "D. C. Sessions" <[email protected]>
> X-Accept-Language: en
> MIME-Version: 1.0
> To: [email protected]
> Subject: Re: [SI-LIST] : How to treat the ASIC package pin-assigns
<snipped>
>=20
> As others have said, your best bet is a differential clock. If you =
can't
> get a differential clock source, at least use a differential receiver=20
with
> an external reference voltage so that your noise sources couple into =
them
> both more or less equally.
>=20
<snipped>
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