Now I ask - take a trace, any trace no matter what it
is and reduce it to it's lumped or non-lumped parameters
of resistance, capacitance and inductance. Look at it
as a "circuit" now and ask yourself if this "circuit"
can actually support a flat BW out to ... whatever it is.
Since board houses measure controlled impedances with
only 1 MHz unless specifically told otherwise,
my bet is no.
A designer may want to argue by way of Shannon's
Theorem that data rates with S/N ratios on the
order of 30 dB or more need only 50 MHz or so BW.
But, edge rates can easily swamp that out very
quickly in terms of orders of magnitude. And with
it, I submit, all of the above also.
Sorry for the lengthy discussion but my point is ...
Put that one circuit in parallel with others and the
odd versus even impedance effects makes this situation
all the worse by changing phase and group velocities.
Thus one ends up with smeared or "slurry" edges. That
in turn *could* effect setups, prop delay, metastability,
and ultimately latency. I'm of course painting a
really worst case scenario.
And as you say, Weber, with the onset of faster edge
rates and fine pitch constructions, we are stuck.
And all we've got so far is trade offs.
Regards, Doug McKean
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