Re: [SI-LIST] : response to semiconductor I/O edge rates

D. C. Sessions ([email protected])
Fri, 16 Jul 1999 09:11:15 -0700

Roy Leventhal wrote:
> Tom,
> The simple answer is that this is a big, proprietary development ASIC. The
> designer never had any intention that it should have such a fast edge rate. As
> a matter of prudent checking he had me check the signal integrity once we got
> the IBIS model and partially routed board. That's when we discovered that the
> edge rate was so fast. The semiconductor house had never given us a heads-up
> that the edge rate was likely to be so fast. Or so I understand it. Now the semi
> house is telling us they can't do anything about it.
> It is possible that the circuit designer knew about the edge rate earlier than I
> think and was hoping that some simulation or layout/routing magic pixy dust
> would be sprinkled on his circuit. I don't think I'll ever know the answer to
> that. I do see wishful thinking about avoiding a conservative (expensive)
> approach to design. Speeds are becoming such that those hopes are rarely
> fulfilled anymore. Even reasonable engineering judgement isn't that great a
> guide anymore and we are contemplating making whole-board simulations part of
> our design process.

It's also possible that the circuit designer did as good a screen as he could
be expected to do without an extensive SI background. Many of us take the
data sheet rise and fall times for standard parts and cells and apply the
Td/5 rule as a screen. This is a perfectly reasonable approach and it would
work if the data sheets didn't lie like a rug thanks to their test conditions.

Personally, I'd LOVE to drive a stake once and for all into the <expletive>
45-pf load test condition. Blow up the cave wall in Texas where it was
found. Hunt down and burn every data book containing it. Et-freaking-cetera.

D. C. Sessions
[email protected]

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