Re: [SI-LIST] : Some Semiconductors are Unnecessarily Fast

Matt ([email protected])
Thu, 15 Jul 1999 16:00:03 -0500

Finally a circuit design side topic to get into..... :)

"D. C. Sessions" wrote:
> "Matt (boomer) Russell" wrote:
> >
> > hi,
> >
> > The problem with the current controlled predriver approach is that
> > to achieve a constant current the gate voltage of the output
> > device needs to be almost constant (very slow) until it goes
> > linear vds<vgs-vt.
> Not really. You use a large device with low gate bias to provide
> the predriver current (remember, this is PREdriver current, not
> final drive current) and switch it with the usual (relatively)
> small devices.

what I mean is that in order for the output transistors to provide
a constant current, it's gate needs to be very slow. Since the
output device is large. This implies a predriver with very low
current, you then have alot of time to get the predriver to go
rail to rail.

> > For a high drive cell with a low cap load (you want the bus
> > to look capacitive [that is the whole point of the edge rate
> > control]) That may be almost all the way across the output swing.
> I think you're confusing output current with predriver current.
> You do NOT want the bus to look capacitive; you don't CARE. What
> you do want is to have the gates of the final drive devices look
> capacitive, and that's easy because that's what CMOS does whether
> we like it or not. Then a steady predriver current (Idsat) from
> the predriver gives a steady dv/dt on the gate of the final drive
> device, which (times Gm) gives a steady di/dt at the pin.

No I mean the output current, the point of this is to get rid of
tline issues on the line you are driving (ie make it looked like
a lumped load). What I am trying to imply is that a steady
dv/dt on the gate of the output device does not create a steady
di/dt on the output of the buffer.

> > This means that your predriver current needs to be very weak
> > which means that the max frequency the IO can support will be
> > very slow if you want the predriver to go full swing (otherwise
> > you start to see data-dependant jitter).
> Because the output switch occurs in a relatively small part of
> the gate charging curve, controlled edge rates ALWAYS impose a
> tradeoff with DJ. Slow-mode USB drivers, with a minimum edge
> time of 90ns, still aren't easy to guarantee full settling in
> 667ns. No big deal -- that's what makes this job fun.

true, but what this is implying is what others have stated in other
messages, you either need a very large library with lots of
speed/slew rate trade off buffers, or a programeable slew rate

USB generally needs some type of AC cap feedback to get something
that slow.

for more normal slew rate control I generally try to waveshape the
predriver output to a more optimal signal then a straight RC rise. :)

> > plus you are assuming a process independant current source
> > for the predriver....
> This was in the context of an external programming resistor, so
> you're absolutely correct. The same results could be obtained
> by tapping a bias current off of the sysclock PLL, though, and
> that would do a nice job of keeping the edge time proportional
> to the cycle time across PVT.

that does work if you know the frequency and pll that will be used.

> > "D. C. Sessions" wrote:
> > >
> > > Mike Degerstrom wrote:
> > > >
> > > > Raymond,
> > > >
> > > > I'd also like to know more about the edge-rate control with use of
> > > > a series resistor as has been mentioned is used with the Analog
> > > > Devices 21020. I have seen mention of parts that use a reference
> > > > resistor to control output impedance, i.e., drive strengths such
> > > > as in the HP article by Esch, and Manley. I also noticed that
> > > > IBM sells SRAMs with programmable impedance control drivers.
> > >
> > > In principal, you can control edge rates by setting the predriver
> > > currents. Output edge rate is mainly dictated by the risetime
> > > of the final driver devices' gate voltages, and that in turn is
> > > dictated by the Ids of the predriver transistors. If you provided
> > > the predriver with a bias voltage to a two-transistor stack (or
> > > three with tristate) such that the switching transistors just
> > > gated the current from the bias transistor the result would be
> > > a controlled dv/dt at the final drive gate and indirectly a
> > > controlled edge rate.
> > >
> > > Since the gate capacitance and transconductance of the final devices
> > > are roughly proportional with process, this approach would give
> > > a reasonably stable output edge rate. Of course there would be
> > > timing impact, and if you controlled the turnoff transistors you'd
> > > have crowbar current. (If you don't control them, then the turnoff
> > > transition could get VERY abrupt, making the net output a bit odd.)
> > >
> > > So it *could* be done, albeit with tradeoffs in power, noise, and
> > > layout complexity.
> > >
> > > --
> > > D. C. Sessions
> > > [email protected]
> > >
> > > **** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at ****
> --
> D. C. Sessions
> [email protected]
> **** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at ****

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