I think we have far underestimated the effect that Andy has just
mentioned. To understand the impedance of any structure, we have to
look at the return path. The path of signal current through a via is
obvious. The path of the return current is not so obvious. A via may
conduct signal current from the top surface clear through to the bottom
surface. There may be several power and ground planes in that PCB or
electronic package stackup. High frequency return current for the via
may go through several dielectric layers as displacement current
(current between the parallel plates of a capacitor). Return current
piling up on power and ground planes causes plane bounce. The distance
to the nearest via that stitches ground planes together is important.
For one via, this effect is not important. The power planes do not
bounce very much due to the current on two 50 Ohm lines connected by a
via. But, supposing we have a whole bus, maybe 64 or more signals,
that each have a via through the same set of power planes. Now we have
64X the return current trying to make it from one return plane to
another, leading to serious plane bounce. The entire return current
may all try to go through a single via that stitches the ground planes
together.
This effect is data dependent. If half the signals switch one
direction and half the other, there is no net return current. If they
all go the same direction at the same time... classic SSN problem.
In this scenario, a singular via will appear to be capacitive (dip in
the TDR waveform). But if you send similar signals through 64 vias,
they will appear to be inductive because all return current is flowing
through the same structure. A hump (rather than a dip) is reflected
back to the source.
As we enter into the era of rise times much less than 1 nSec and source
synchronous busses, we will have to pay much closer attention to the
return current path and power plane bounce in order to preserve the
fast edges.
regards,
Larry Smith
Sun Microsystems
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