[SI-LIST] : edge-rates and vias

Jan Vercammen ([email protected])
Wed, 14 Jul 1999 13:06:31 +0200

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I would like to comment on two topics that have been circulating lately: edge-rates
and vias as a discontinuity.

I have measured 20-80% edge-rates of various logic families (january 1995) for both
high impedance (500R passive probe), low impedance (100R to terminator voltage VT=2.2V
or 83R to 1.5V) or the standard capacitive load (50pF+500R). All were measured with a
50R 1GHz bw digital scope using a high-frequency PCB fixture. The scope is calibrated
and has a reported t_rp=330ps pulse response time (10% to 90%).

All edge rates are 20% to 80%. A Texas 74AS and 74ALS gate, a CMOS Quality Semiconductor
FCT and FCT 8-bit buffer (internally 25R) and a Texas 16-bit wide ABT buffer were measured.
Additionally I also measured a Motorola ECL Eclips (using pseudo ECL voltage levels).

Recently I have also measured a Motorola PLL clock generator (Mot980), a spread spectrum
clock generator W42C32-05 clock output (8mA driver) and two Texas buffers CDC328 (bipolar
type +/-64mA spec) and CDC329 (CMOS type +/-48mA). The clock drivers (Mot980 and CDC328/329)
were measured with a 1K probe but driving a 50R line using series termination, the W42C32-05
was measured with a 1K passive probe (again using the same 1GHz scope).

I leave the numbers for themselves. However, one can draw some conclusions:

- almost all UNLOADED devices have subns rise/fall times
- extra loading (capacitive or by a transmission line = resistive) will, in general, enlarge the
rise/fall time to above 1ns, except for the high-current buffers and clock drivers
- the detailed behaviour could be very specific: type (CMOS, bipolar), process dimensions, ...

Some additional remarks:

- I find the 10%-90% marks often difficult to use because they fail to give a good indication
of the derivate of the output voltage with respect to time, the 20%-80% marks are better in this
respect
- the finite pulse respons of our scope does influence some results and we should correct some
of the data, obviously a measured 320ps rise time translates into something faster. Normally I use
t_real = sqrt(t_meas*t_meas-t_rp*t_rp), even though the pulse respons time t_rp is for 10%-90% only
and not for a 20%-80% rise time. Does anyone know how to use a 10%-90% t_rp to correct a measured
20%-80% rise time??????

I would also like to share some results from measurements on a signal and pin vias on a 6-layer PWB
test vehicle. The measurements were done with a HP 18A18, a 25 year old TDR, which still produces
remarkable clean and fast edges (90s)! I do not have the finances for better equipment with the usual
signal processing (gating, normalisation, ...), so these are engineering estimates. I have listed
my data for several signal vias (standard vias and testpad types).

Note: diam = diameter, mil=25.4micron, the "plane clearence diam" is the diameter of the power or
ground plane clearence around the pin. Actually, more parameters are involved in describing a via in the
PWB technology file, but I have simplified this data somewhat.
estimated
via type | drill diam | top/bottom pad diam | plane clearence diam | capacitance
--------- ---------- ------------------- -------------------- -----------
signal via 11mil 31mil/31mil 45mil 100fF
signal via #1 11mil 31mil/31mil 73mil 75fF
testpad via 11mil 31mil/47mil 45mil 125fF
testpad via #1 11mil 31mil/47mil 73mil 75fF
testpad via #2 11mil 31mil/47mil 89mil 50-75fF

The PWB technology used is 5mil (125micron). The vias tested are signal vias with a drill diameter of
11mil and different top/bottom pads for the testpad via (which is probed by in-circuit testers from the
bottom). Also the clearence to the power planes (gnd and vcc plane) were varied. Both the pads and the
plane clearence on the vias have small effects, but neglible effects for our range of applications. Smaller
pads and a largere clearence reduces the capacitance.

My experience is that small signal and testpad vias look like capacitors, albeit small ones. There is
obvious a difference if you use a signal via to switch from layer 1 to layer 2 (and stay on the same PWB
site), in contrast to vias that take signals through the power planes (of course all vias, except blind and
burried vias, penetrate the PWB, but not all take a signal through the power planes!). I have done some
investigations on these kind of power-plane signal-penetrating vias and my preliminary conclusions are
that they also show the capacitive behaviour (quallitative and quantitative) of the non-signal-penetrating
vias, but it is possible that there are subtle differences. The TDR traces between the two look slightly
different (in the tail of the capacitive reflection), however, this is only a preliminary conclusion and,
possibly, a misinterpretation or an incorrect measurement. I do not want do go deeper into this matter
for now.

Regards,

Jan Vercammen
EMC/PCB Engineering
Agfa-Gevaert
[email protected]

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