Some additional thoughts & questions:
I use Cadence's SpecctraQuest/SigExplore to simulate the boards. Those tools use
IBIS I/O cell models. SPICE models would cause me lots of extra time and effort
to get into IBIS format. We have found topology simulation, timing guided
placement, impedance guided routing, etc. to be all very helpful.
I STRONGLY advocate sanity checks very early in the process. For such checks can
we get "+/-20%" models early on?
There are several caveats. Of course we don't want to get into "you said - - - "
finger pointing of early, first cut models. Then too, I would guess that IBIS
models give you no process control information feedback. Lastly, more complex
topologies need more accurate, worst case models not usually avilable early on.
Unless you're designing into a standard process.
What's your ideas on dealing with these issues?
Roy
**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****