Re: Re[2]: [SI-LIST] : Via Capacitances ...

Douglas McKean ([email protected])
Mon, 12 Jul 1999 10:21:05 -0700

Very interesting. For those who would like
some theory behind this post, allow me to
give a short explanation ...

Suppose we have the following construction:

< Z1

Anticipating the type of line termination
reflection can be calculated by using

Z1 - Z0
Tau = -------
Z1 + Z0

Case 1: Z1 = Z0
Therefore, Tau = 0
No reflections.

Case 2: Z1 >> Z0, Z0 = 0, or Z1 = infinity
Therefore Tau ~ 1
Any reflections are positive in nature.

Case 3: Z1 << Z0, Z1 = 0, or Z0 = infinity
Therefore, Tau ~ -1
Any reflections are negative in nature.

What Mr. Cheong has demonstrated is that vias
are of a Case 3 nature.

I have strongly suspected that vias are also of
a differentiator model when Z0 is not equal to Z1.
With Z0 = Z1 it appears as a classic delay line.

Zo Z1


Regards, Doug McKean

At 09:46 AM 7/12/99 -0500, [email protected] wrote:
>I agree with Ron's email on via being nothing but a capacitive stub.
>One can verify that by measuring a typical via with a TDR.
>Run a length of trace with an open via in the middle and launch a TDR signal
>(~35pS) from one end. Make sure the line is terminated in its characteristic
>impedance. You will discover a negative reflection (capacitive
>The equivalent capacitance can be derived by utilizing the reflected voltage,
>risetime, incident voltage and Zo.
>Michael Cheong

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