BTW, Tom also gives a great presentation with
a breakdown of the measured edgerate characteristics
of various devices.
regards,
scott
tomda wrote:
> Assume 100 to 500 psec for the full transition for any modern logic family
> unless it has controlled edge rates.
>
> Tom Dagostino
>
> -----Original Message-----
> From: Ken Patterson [SMTP:[email protected]]
> Sent: Thursday, July 08, 1999 12:07 PM
> To: [email protected]
> Subject: [SI-LIST] : Edge Rates
>
> I am a newcomer to signal integrity analysis and would like to know how
> to find out what the typical edge rates (i.e. rise and fall times) of
> some of the industry standard logic families are. These include FCT
> logic, SDRAMs and Syncburst SRAMs . I have an upcoming project that
> will use these devices and would loike to perform some signal integrity
> analysis.
>
> Ken Patterson
> Electronic Engineer
> ADC Broadband Communications/Pathway Division
> email:[email protected]
>
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