An Intensive Three-Day Short Course
San Jose, California
October 20-22, 1999
Offered by
Raj Mittra/Penn State, Paul Franzon /N. C. State, and Dale Becker/IBM
Poughkeepsie
UNDER THE SPONSORSHIP
OF
THE NORTHEAST CONSORTIUM FOR ENGINEERING EDUCATION (NCEE)
ELECTRICAL MODELING, SIMULATION, AND DESIGN OF INTERCONNECTS
COURSE DESCRIPTION
This three-day short course will provide an in-depth coverage of
numerous aspects of electrical modeling, simulation and design with
emphasis on 'on-chip" interconnects.
Various design options will be discussed and the electrical issues
in interconnect design will be identified. Detailed design procedures
will be outlined and the use of CAD/CAE tools for interconnect layout wil=
l
be described.
Techniques for electromagnetic modeling and simulation of
interconnects, multi-conductor transmission lines, and discontinuities in
these lines, e.g., crossovers, bends and vias, will be presented.
Methods for estimating the power and ground plane noise also will
be discussed.
LECTURERS
Dale Becker received his Ph.D. in Electrical & Computer Engineering from
the University of Illinois. He is currently a Senior Engineer in the
System 390 Division of IBM in Poughkeepsie, NY. He leads the MCM design
team that integrates and implements the multiprocessor design for IBM's
large server platforms. Dr. Becker's current interests focus on the
electrical design of the components that comprise a high-frequency CMOS
processor system. He specializes in the application of electromagnetic
numerical methods to the issues of signal integrity and simultaneous
switching noise in electronic packaging, the measurement of these
phenomenon, and the verification of the models.
Paul Franzon is a Professor in the Department of Electrical and
Computer Engineering at North Carolina State University. He has ten years
of experience in electronic systems design and design methodology researc=
h
and development, including working at AT&T Bell Laboratories, and as the
founding member of a communications company. Dr. Franzon's current
research interests focus on the design sciences/methodology for high-spee=
d
packaging and interconnect, and also for high-speed and low-power chip
design. He is a consultant to a number of companies in these areas and
has extensive experience in teaching related professional courses.
Raj Mittra is a Professor in the Department of Electrical Engineering at
the Pennsylvania State University and Director of the Electromagnetic
Communication Research Laboratory. He has directed many short courses on
Electronic Packaging and Computational Electromagnetics, both in the U.S.
and in Europe, and has offered on-site seminar series at several
industrial locations including GTE Network Systems, Cray Research, DEC,
IBM and Intel. He has authored and co-authored over 508 research papers
and has contributed to or edited 35 textbooks. He has served the IEEE AP-=
S
Society as a National Distinguished Lecturer, as President, and as an
Editor of the IEEE Transactions on Antennas and Propagation. He also head=
s
RM Associates, a company that provides consulting services to many
government and industrial organizations.
COURSE OUTLINE
DESIGN INTRODUCTION
( Introduction:
* Overview of interconnect hierarchy
* Signal integrity and synchronous design
UNDERSTANDING AND ANALYSIS OF ELECTRICAL INTERCONNECT STRUCTURES
* Deciding on model fidelity.
Transmission line vs. other models, skin effect
* Sources of noise and signal degradation and their control.
Reflection, crosstalk, SSN other common mode noise sources and control
( Introduction to EMC
DESIGN OF ELECTRICAL INTERCONNECT STRUCTURES AND CIRCUITS, ELECTRICAL
DESIGN OF PACKAGING, BOARDS, AND MCMS
* Interconnect decision making.
Noise budgeting, eye diagrams.
* Package decision making.
Criteria, techniques, CAD tools.
* PCB layout and termination issues.
Noise budgeting, CAD tools.
* Cable issues.
Modeling.
* On-chip interconnect delay and noise issues.
Differences to package level. Design and extraction issues.
Signal Distribution Modeling and Simulation
? Principles of signal integrity (SI)
? Low-loss interconnects
? Application to on-chip high-loss interconnects
? Unique SI issues for on-chip interconnects
The role of inductance and wide buses at high-frequencies
? Modeling and extraction issues
* Model development and verification
* The application of available extraction tools to existing design
? Noise and timing budgets
Power Distribution Modeling and Simulation
? Noise components
Simultaneous switching noises (I/O); Core switching noise;
Power transients; Frequency response and resonances
? Modeling considerations
Partitioning for modeling and simulation tools; Modeling on-chip power
distribution; Predicting voltage and ground variations at the circuit
? Decoupling strategy
Noise budgets and limits; Capacitor choice on-chip and off-chip; Capacito=
r
placement
? Measurement and verification
System Design Considerations
* Case study of a CMOS multiprocessor server implementation
Integrating SI methodology into the chip and package design tools;
Balancing the budgets ? Power, Noise, Timing, Clock Skew; Modeling tools;
Verification and validation
Methods for Capacitance Computation of On-chip Interconnects
* Overview of Interconnect Capacitance Computation
* Electric field; electrostatic potential; Gauss's Law; Laplace's and
Poisson's equations; capacitance of multi-conductor systems
* Method of moments and the boundary element method; application to
capacitance calculations for single and multiple lines; three-dimensional
capacitance calculations
* Introduction to finite element method (FEM); application to capacitance
and inductance calculations for uniform and multiple lines with etches of
arbitrary cross-section; extension to three-dimensional calculations of
complex geometries
* Efficient Finite Difference Method for general-purpose of interconnects=
;
Capacitance Computation; Techniques for speeding up the computation of
large, complex, interconnect structures
* Inductance calculation of interconnect structures
Comparison and Code Descriptions
* Comparison between various modeling approaches and recommendations as t=
o
when to use what
* Brief descriptions of available computer codes
Power plane Noise Modeling
* Electrical modeling of single and multilayer power planes
* Computation of Leff and equivalent capacitance of power planes
* Application to the estimation of delta-I noise
GENERAL INFORMATION
To register: Early registration is advised. Complete and return the
Registration Form or phone the registrar, Kelly Brown, at 407-892-6146, o=
r
FAX 407-892-0406, or e-mail at: [email protected] (note number 1 not
letter el before @). For technical information telephone Raj Mittra at
814-865-1298, or FAX 814-865-1299, or e-mail: [email protected] (note
number 1 not letter el after R); Paul Franzon at 919-515-7351, or e-mail:
[email protected]; Dale Becker at 914-435-6735, or e-mail:
[email protected].
Attendance is limited. Register early to guarantee your course materials.
Fee: The registration fee is $1,100.00 for the course. This fee includes
all course materials and refreshment breaks.
Schedule: Registration and check-in will be from 8:30 a.m.- 9:00 a.m. on
the first day. The seminar hours will be 9:00 a.m. - 12:00 noon and 1:30
p.m. - 4:30 p.m. each day.
Location: The course will be held at the Radisson Plaza San Jose -
Airport, 1171 North Fourth Street, San Jose, CA 95112.
Lodging: If you need overnight accommodations, contact the Radisson Plaz=
a
Jose - Airport, at 408-452-0200. Be sure to mention that you are attendin=
g
the "Electrical Modeling, Simulation, and Design of Interconnects" course
to receive the special conference rate. Reserve your room before
September 19, 1999, to be guaranteed the special conference rate.
Continuing Education Units: This program will be assigned 4 Continuing
Education Units (CEU's). A certificate of course completion will be
awarded.
Substitutions and Refunds: Substitutions may be made at any time. If for
any reason whatsoever you cannot attend, the entire tuition fee, minus
$25.00 administration fee, will be refunded if cancellation is received
before the start date of the course, and no refunds will be made after
that. Please register early.
In-house program: This program is also available for on-site
presentations. If you are interested in a tailor-made program to be
offered at your company site, please call Raj Mittra at 814-865-1298 for
further information, or contact via fax/e-mail.
Electrical Modeling, Simulation And Design Of Interconnects October
20-22, 1999 =95 San Jose, California
THE NORTHEAST CONSORTIUM FOR ENGINEERING EDUCATION (NCEE)
REGISTRATION FORM Attendance is limited. Please register early.
Last Name (Please Print) First Name Middle
Initial E-mail Address (Please Print)
Institution/Organization Title/Position
Address
City State Zip + 4
Area Code Home Phone Area Code Business Phone Fax
Check appropriate item: Make checks payable to: Return this form to:
NCEE (Interconnects Course) NCEE
Central Florida Facility - Management Office
____ $1,100.00 registration fee enclosed 1101 Massachusetts
Avenue
St. Cloud, FL 34769
____ Bill me/my organization
(Billing authorization enclosed) Attention:
Registrar's Office; Kelly Brown, Registrar
____ Purchase order enclosed Phone: 407-892-6146;
FAX: 407-892-0406
NCEE Central Florida Facility
1101 Massachusetts Avenue
St. Cloud, FL 34769
Mailroom:
If the person on the label is no longer at this location, please route
this informative brochure to his/her replacement or department manager.
Route To:
--=20
---Paul Franzon, Professor, North Carolina State University
919 515 7351, fax. 919 515 2285, www.ece.ncsu.edu/erl/faculty/paulf.html
Rm. 443, Engineering Graduate Research Center, Centennial Campus
smail: ECE, Box 7914, NCSU, Raleigh NC 27695-7914
Fedex: Rm. 419, EGRC, 1010 Main Campus Dve, NCSU, Raleigh NC 27695-7914
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