# Re: [SI-LIST] : 20-H Rule for Power Planes

Larry Smith ([email protected])
Thu, 27 May 1999 16:05:12 -0700 (PDT)

Never the less, it is the EMI engineer's very difficult job is to
identify some node or nodes in the logic circuitry for attachment to
the frame. Depending on where you look, there is likely to be 10's or
100's of AC mVolts on logic Vdd WRT logic Gnd, across the power
planes. And as you have pointed out below, 1 mV of noise on the frame
WRT earth ground can be an EMI disaster. Which power plane is moving
WRT spice 0? It completely depends on where you choose to put spice
node 0.

After thinking about the conversation in this thread a little more,
perhaps it is possible for the EMI engineer to "define" spice node 0 by
the connection of frame ground to logic ground. It wouldn't matter if
he chose the Vdd plane or the Gnd plane to do this, but it should be
consistent with "safety Gnd", so the Gnd plane is more desireable. If
the SI engineers have done thier job well, there should be very little
current flowing from logic Gnd to frame Gnd. Even though the
connection between frame and logic Gnd is likely to be a high impedance
compared to the impedance between logic Gnd and Vdd, there should be
little current in the high impedance connection, therefore little
voltage. By the same argument, a high impedance connection from the
frame to earth ground might keep the frame ground well behaved.

Now that we have defined a preferential power plane, it might make
sense to build a 'psudo faraday cage' with the prefered plane extending
out beyond the noisy power plane (20-H Rule). The thing that bothers
me about this is that now all the Vdd structures have a voltage WRT the
prefered Gnd structures which are somewhat tied to earth ground. It
seems like we have taken differential volages and turned them into
common mode.

Well, I think I will go back to what I do best (SI) and leave the EMI
to the experts. Enough fun for one week, I'm AFK for the weekend.
(don't your weekends start on Thursday??)

regards,
Larry Smith
Sun Microsystems

> X-Sender: [email protected]
> Date: Wed, 26 May 1999 18:36:57 -0700
> To: [email protected]
> From: John Lockwood <[email protected]>
> Subject: Re: [SI-LIST] : 20-H Rule for Power Planes
> Mime-Version: 1.0
>
> Hi Larry,
>
> I am joining in a little late here - but I thought I'd add my 2 cents
> worth. You guys seem to be having too much fun.
>
> First of all, in a reasonably well designed enclosure your shield had
> better be as close to a "spice node 0" as you can get or you won't pass
> radiated emissions. At the open field site cables or wires(exiting the box)
> which have a voltage differential relative to chassis will radiate. It only
> takes something on the order of 1 mv to put you at the FCC A limit.
>
> Knowing this, your friendly EMC engineer has referenced various logic
> ground points near I/O to the chassis (like near the wire I mentioned
> above). Knowing where to short chassis and ground is key here. Now chassis
> and ground are now very close to the same potential( at that point), but
> power is very noisy relative to them. If that power comes too close to a
> trace leading to the wire exiting the box it couples and radiates. I have
> had this happen with 100BaseT differential pairs. We fixed the radiated
> emissions failure by doing nothing other than cutting back the power plane
> in that area.
>
> Another way of saying this is that the EMC engineer who has shorted chassis
> to ground a various points has made ground preferential. In your example of
> a laptop they may have done a good enough pcb layout that they don't have a
> full chassis, but they do have a metal I/O panel for their cables and they
> have bolted it to the ground plane.
>
> In a different product the edge of the power plane was very closely coupled
> to a card guide that was not well grounded to the card. Even though the
> power plane was cut back 20h we were having emissions problems related to
> the power plane. The emissions went away when we completely sealed the
> power within the ground planes by connecting the top ground plane to the
> bottom ground plane along that edge of the card with copper tape. The
> original board had the ground planes stitched together every 0.2" along
> that edge. That was not good enough.
>
>
> John Lockwood
> Juniper Networks

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