ftp://ftp.cadence.com/pub/timing101a.zip
Todd.
At 12:02 PM 5/27/99 -0400, you wrote:
>Andrew,
>
>You should somehow get allowance for the test load. Some simulators
>automatically adjust your timing results for the difference in test load and
>actual load. If yours didn't, then I believe you're right - you have a 2.5ns
>credit.
>
>best regards,
>Jim
>
>-----Original Message-----
>From: Andrew Phillips [mailto:[email protected]]
>Sent: Thursday, May 27, 1999 10:02 AM
>To: SI-LIST
>Subject: [SI-LIST] : question about timing analysis
>
>
>
>Hello,
>
>Have been doing some IBIS simulations of a circuit to determine
>interconnection delays and whether they are small enough to satisfy
>timing requirements. The datasheet for the device driving the circuit
>states that all timing parameters are quoted as if the driver was
>connected to a 50ohm series resistor and a 30pF load.
>
>Now, when I simulate the driver connected to this load it shows that
>rise and fall waveforms at the load take 2.5ns to reach threshold
>voltages.
>
>Instead of having this test load I (of course) actually have my specific
>circuit. The voltages at the load now take 5ns to settle.
>
>The driver is an address line going to a SDRAM. The datasheet for the
>driver says that the address is valid 6ns after a clock.
>
>Here's the question - to determine whether the address will be settled
>in time at the SDRAM input is it safe to assume that I can subtract the
>2.5ns (for the test load) from the address valid timing spec and instead
>add the settling time of my actual circuit (i.e. address valid after
>clock = 6ns - 2.5ns + 5ns = 8.5ns) ??
>
>Thanks for any help,
>
>Andrew Phillips
>Supercomputing Systems AG
>Zurich, Switzerland
>
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>
>
<excerpt><bold>
</bold></excerpt> <bold>Todd Westerhoff
</bold><color><param>0000,0000,ffff</param> Technical Marketing
Director | High Speed Systems Design | Performance Engineering
</color><color><param>ffff,0000,0000</param> Cadence Design Systems |
270 Billerica Road | Chelmsford, MA 01824
</color>
ph: (978) 262-6327
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email: [email protected]
internal information website: http://www-ma.cadence.com/~toddw
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