Yes. By subtracting out the time the driver takes to reach
threshold with the standard test load, you calibrate your
simulation to the test circuit.
Technically, you subtract the time that the in-circuit simulation
crosses threshold at the receiver from the time that the test
load simulation crosses threshold at the driver to obtain your
loaded flight time. (The manufacturer only guarantees timing to
the test load.) This can then be placed in your setup and
hold timing equations to determine if you meet spec.
Regards,
Scott
Andrew Phillips wrote:
> Hello,
>
> Have been doing some IBIS simulations of a circuit to determine
> interconnection delays and whether they are small enough to satisfy
> timing requirements. The datasheet for the device driving the circuit
> states that all timing parameters are quoted as if the driver was
> connected to a 50ohm series resistor and a 30pF load.
>
> Now, when I simulate the driver connected to this load it shows that
> rise and fall waveforms at the load take 2.5ns to reach threshold
> voltages.
>
> Instead of having this test load I (of course) actually have my specific
> circuit. The voltages at the load now take 5ns to settle.
>
> The driver is an address line going to a SDRAM. The datasheet for the
> driver says that the address is valid 6ns after a clock.
>
> Here's the question - to determine whether the address will be settled
> in time at the SDRAM input is it safe to assume that I can subtract the
> 2.5ns (for the test load) from the address valid timing spec and instead
> add the settling time of my actual circuit (i.e. address valid after
> clock = 6ns - 2.5ns + 5ns = 8.5ns) ??
>
> Thanks for any help,
>
> Andrew Phillips
> Supercomputing Systems AG
> Zurich, Switzerland
>
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