Re: [SI-LIST] : 20-H Rule for Power Planes

John Lockwood ([email protected])
Wed, 26 May 1999 18:36:57 -0700

Hi Larry,

I am joining in a little late here - but I thought I'd add my 2 cents
worth. You guys seem to be having too much fun.

First of all, in a reasonably well designed enclosure your shield had
better be as close to a "spice node 0" as you can get or you won't pass
radiated emissions. At the open field site cables or wires(exiting the box)
which have a voltage differential relative to chassis will radiate. It only
takes something on the order of 1 mv to put you at the FCC A limit.

Knowing this, your friendly EMC engineer has referenced various logic
ground points near I/O to the chassis (like near the wire I mentioned
above). Knowing where to short chassis and ground is key here. Now chassis
and ground are now very close to the same potential( at that point), but
power is very noisy relative to them. If that power comes too close to a
trace leading to the wire exiting the box it couples and radiates. I have
had this happen with 100BaseT differential pairs. We fixed the radiated
emissions failure by doing nothing other than cutting back the power plane
in that area.

Another way of saying this is that the EMC engineer who has shorted chassis
to ground a various points has made ground preferential. In your example of
a laptop they may have done a good enough pcb layout that they don't have a
full chassis, but they do have a metal I/O panel for their cables and they
have bolted it to the ground plane.

In a different product the edge of the power plane was very closely coupled
to a card guide that was not well grounded to the card. Even though the
power plane was cut back 20h we were having emissions problems related to
the power plane. The emissions went away when we completely sealed the
power within the ground planes by connecting the top ground plane to the
bottom ground plane along that edge of the card with copper tape. The
original board had the ground planes stitched together every 0.2" along
that edge. That was not good enough.

John Lockwood
Juniper Networks

At 02:10 PM 5/26/99 -0700, you wrote:
>Michael - You are correct that there will be fringing fields between
>power planes at the edges of a PCB. My major point is that neither the
>Vdd plane nor the Gnd plane is preferential. They are both power
>planes that have a differential voltage between them. If they are in a
>laptop computer, one plane could easily have 1000V and the other plane
>1003.3V WRT earth ground, especially if I walk around on a carpeted
>floor while holding it.
>There is no "spice node 0" even in systems that are tied to earth
>ground with a copper telephone pole driven into the earth and connected
>to the frame with a 2 inch bus bar. The impedance of the earth ground
>connection is still much higher than the impedance between power
>Every voltage measured in a digital system is measured differentially
>WRT some other point in the digital system. Single ended oscilloscope
>probes measure the difference in the voltage between the measurement
>point and the point where you attach the probe ground. (We have to be
>a little careful of ground loop currents but they are usually much
>lower frequency than the frequencies we care about.)
>Even in well grounded systems, I don't think there is any preference
>between the Vdd and Gnd plane at high frequencies, so I am not sure
>which plane to make 20-H larger than the other plane.
>But let's take a closer look at the fields at the plane edges. At
>every xy location of the power planes, a differential voltage could be
>measured. At low frequency, you get the same measurement at every
>location. At higher frequencies where the board size is significant
>compared to the wavelength, you begin to get different voltages
>depending on the xy location of the measurement.
>One particularly interesting frequency is the one where 1/2 wavelength
>fits into the length of the board (250 MHz for a 12 inch FR4 board...
>hmmm, pretty close to where I live...). This is a cavity resonance,
>boundary value problem. We know that the current in the copper planes
>is zero at the edge of the board (open circuit), therefor the voltage
>fields are at a maximum. Going back to a transmission line analogy for
>a 1/2 wavelength resonator, we know that the differential current
>(difference between the current in the Vdd plane and Gnd plane) in the
>middle of the board is at a maximum and the differential voltage is 0.
>This explains why power planes have resonant peaks at frequencies
>associated with 1/2, 1, 3/2, 2... wavelengths. The differential
>voltage at the power plane edges will be maximum at those frequencies
>and the differential current will be 0 (edge of the board). Istvan
>Novak has done some interesting work in terminating the edges of these
>power planes in order to stop the resonances.
>If the edges are not terminated or damped by some other means, we
>have potential EMI issues from voltages and currents on the power
>planes. Suppose we make one plane larger than the other. The current
>stops at the edge of the smaller plane. The larger plane sees a major
>impedance discontinuity at the edge of the smaller plane, but some
>current keeps going to the edge of the larger plane. It is _not_
>differential current. It is a one way current whose return path is
>displacement current in the FR4 or air.
>A voltage is developed at the edge of the larger plane that is not
>balanced by a voltage on a nearby plane. In fact, the nearest
>reference is 20H away instead of 1H. We have just changed nice
>differential currents and voltages on a set of well behaved power
>planes into common mode voltages and currents. Not a good thing to do
>if we are trying to prevent EMI.
>Larry Smith
>Sun Microsystems
>> From: Michael E Vrbanac <[email protected]>
>> Subject: Re: [SI-LIST] : 20-H Rule for Power Planes
>> To: [email protected]
>> Date: Tue, 25 May 1999 18:50:40 -0700 (PDT)
>> Cc: [email protected] (Michael E Vrbanac)
>> MIME-Version: 1.0
>> Content-Transfer-Encoding: 7bit
>> Larry,
>> Interesting proposition....
>> The fields do exist and have been shown to be troublesome whether you
>> believe in the rule or not.
>> Judging from the assumptions that you have presented, you certainly
>> could have a bigger problem than fringing field radiation/coupling. You
>> probably won't need to worry about the 20H rule. That indeed won't be
>> the bigger issue in that case.
>> Which brings me back to the point I mentioned earlier... it depends
>> on "the design criteria"... "how much", how you implement your system
>> design, etc.
>> BTW, the plane that is larger in the 20H rule is the one connected to
>> system reference. For folks who do not reference planes to the system
>> reference, then the rule is not usable. The fringing field will
>> remain uncontrolled (the 20H rule applied in the PCB would be pointless
>> as the whole board assembly now becomes the energized element in the
>> "planar structure" generating the fringing field) and other
>> methods/intervention must be used to alleviate any problems arising
>> from the situation.
>> re: differential circuits, common mode current, et al
>> I think one would be hard pressed to define the typical digital signal
>> as purely differential unless the driver/receiver and transmission line
>> constructs are specifically built that way. The last time I looked,
>> most of that is "single ended or unbalanced" and not "differential
>> or balanced".
>> re: common mode radiation
>> The basic model for common mode radiation is an "energized element"
>> against a ground reference which typically happens when cable shields
>> aren't grounded to chassis and signal grounds do not have low
>> impedance attachments to the system reference (i.e. chassis)... hence
>> my comment above that the situation for a system like this does not
>> need to worry about the 20H rule in a PCB as a primary problem... it will
>> likely have more serious electromagnetically related issues elsewhere.
>> I will concede that controlling those issues in such a case is
>> possible but certainly more difficult and oftentimes more expensive.
>> Regards,
>> Michael E. Vrbanac
>> >
>> > I don't believe in the "20-H Rule". Suppose the power plane was at
>> > 3.3V and the ground plane was at 0V. It would be easy to reconfigure
>> > the system so that the "power" plane is at 0 volts and the"ground"
>> > plane is at -3.3V. Does this mean that the power plane should now be
>> > bigger than the ground plane?
>> >
>> > The only difference between the power and ground plane is that one is a
>> > 0V and the other 3.3V WRT (...thats with respect to, lest I start
>> > another discussion...) earth ground. But even this is not true in a
>> > battery operated system. In any modern digital system, the impedance
>> > between the power and ground plane is much less than 1 ohm well into
>> > the EMI frequencies.
>> >
>> > The ground plane probably has a path out to frame ground and eventually
>> > earth ground somewhere. But if that path is more than an inch long, it
>> > is going to be well over 10 nH. Ten nH is 1 Ohm at 15 MHz (Z=jwL) and
>> > higher impedance at higher frequencies. So, above 15 MHz, the voltage
>> > between the power and ground planes is insignificant compared to the
>> > voltage across the earth ground connection.
>> >
>> > The power and ground planes should be exactly the same size. To make
>> > one larger than the other will simply have the effect of turning nice
>> > diffential currents into common mode current and common mode
>> > radiation.
>> >
>> > regards,
>> > Larry Smith
>> > Sun Microsystems
>> >
>> >
>> > > From: Mark Freeman <[email protected]>
>> > > To: "'[email protected]'" <[email protected]>
>> > > Subject: [SI-LIST] : 20-H Rule for Power Planes
>> > > Date: Tue, 25 May 1999 10:09:37 -0700
>> > > MIME-Version: 1.0
>> > > Content-Transfer-Encoding: quoted-printable
>> > >
>> > > Now and again I come across references to the "20-H Rule" for reducing
>> > power planes. This rule states that the power plane should be smaller
>> > plane; The power plane edges should be back from the power plane a
>> > the plane spacing. This reduces fringing fields from the power plane
>> > coupling to adjacent planes and free space.
>> > >
>> > > Best I can tell, this rule originated with Mike King. The earliest
>reference I
>> > is Mark Montrose's "Printed Circuit Board Design Techniques for EMC
>> > 26. I have not found any numbers - analytical, simulation or
measurement -
>> > indicate the effectiveness of this technique over frequency.
Intuition (a
>> > thing for this digital designer to rely upon) tells me that the
>of the
>> > fringing fields are small, thus only affecting GHz-range signals. Is
>> > currently only of interest to cell 'phone designers, or do we need to
>> > this technique to digital PBW design?
>> > >
>> > >
>> > > Mark Freeman
>> > > [email protected]
>> > > Stratos Product Development, LLC
>> > >
>> > >
>> > >
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