Re: [SI-LIST] : Decoupling caps and power plane effects

Mike Degerstrom ([email protected])
Mon, 17 May 1999 14:20:52 -0500


I think you are on the right track with respect to modeling
the power distributions. What I have done in the past is
to model the power/ground planes as a one-dimensional radial
transmission line which is built from RLC subsections. Say
for example you have an chip in the middle of a PCB. I don't
know your output edge rates, but I'll assume 1 nanosecond. I
will also assume your chip is digital and that N outputs switch
off the chip. I simply model a "super-buffer" with multiplicity
of N. Then I'll compute the total pcb capacitance within
(1 ns)/10 which is ~0.5" from the chip (assuming ~200ps/inch).
>From this capacitance I can use telegraphers equations to calculate
the "ESL" of that section of the board within 0.5" of the board with
the formula:

Lboard,0.5" = Cboard,0.5" * (100ps)^2

The resistance of the board can also be equally calculated to complete
the first RLC subckt of the radial transmission line. Now you
can compute more RLC subckts for those portons of the board
that are from 0.5" to 1.0" from the ASIC, from 1.0" to 1.5"
from the ASIC and so on until the radial transmission line
is completed. If you have M decoupling caps within 0.5" of
the pcb and these caps have their own RLC model then create an
effective decoupling cap model with R/M, L/M, and C*M for parallel values.

I know I left out much detail and I can elaborate on the details
if you'd like. The approach I outlined is very simplistic and I will
tend to worse case the analysis to compensate for the simplicity.
However, one can really learn alot in a short amount of time
using this this approach by quickly changing model parameters
such as ESL of the caps, the number of caps, the pcb power
ground requirements, and so on.


On May 17, 10:55am, Bermensolo, Todd L wrote:
> Subject: [SI-LIST] : Decoupling caps and power plane effects
> To calculate the required number of decoupling capacitance for a given
> motherboard, I am trying to setup lumped RLC circuit to model the behavior
> of a realistic capacitor discharging into a power plane. The modeling of
> the realistic capacitor just involved RLC elements all in series. The ESR
> is determined from the vendors datasheet. The ESL from the datasheet as
> well as the loop inductance when placed on the PCB. To model the presence
> of the power plane is proving more involved.
> When a chip on a circuit board has its initial current draw from its outputs
> switching, the power plane is the first to respond with current. This is
> due to the low inductance of the power plane. Next the ceramic capacitors
> respond, followed by the higher ESL caps and then finally the power supply.
> The effect of the power plane responding to the IC's current draw is the
> topic which I would appreciate assistance on. At time t=0, an IC chip's
> outputs switch and its power pins will draw a current Io from the power
> plane of a motherboard. Since the power plane is essentially a large
> capacitor, its discharging current will decrease the voltage level of the
> plane until the ceramics respond to stabilize...then the bulks...then the
> power supply. The rate at which the power plane discharges is of interest
> to me. If the effective capacitance of the power plane seen by a chip can
> be gauged, then the discharge rate of the power plane supplying current to
> some load can be modeled with a lumped capacitave element. With the
> discharge of the power supply predictable, then decoupling capacitance can
> be calculated to prevent the power plane voltage from drooping below a
> specified voltage.
> Has anyone done any power/ground studies that would shed light on this
> problem? Are any of my assumptions invalid?
> Thanks all.
> Todd Bermensolo
> Intel Corp
> High End Server Division
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>-- End of excerpt from Bermensolo, Todd L

Mike Degerstrom         Email:    [email protected]	
Mayo Clinic 
200 1st Street SW 
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