Re: [SI-LIST] : Looking Inside IBIS Model

Syed Huq ([email protected])
Sat, 15 May 1999 21:43:14 -0700 (PDT)

Your comments are correct. Too many times we have seen IBIS model without
the timing parameters(Vmeas, Vref, Rref and Cref). The vendors reasoning is that
they are 'optional' so they left it out. We always have to go back and stress
the need for these for accurate TIME_TO_VM(Quad, XTK)calculation. In most
cases, it was basically a lack of understanding of what an end user does with
IBIS models.

Timing analysis is a key part of all SI simulations.

These test load must match the datasheet specified loads. Datasheet numbers
are what the vendors are guranteeing.

Cisco Systems, Inc

> To summarize, test load and test fixture parameters are not
> equivalent. When Vmeas, Vref, Rref, and Cref are accurately specified
> for a driver model, consistent with the datasheet, then they represent
> valuable information which can facilitate the timing synchronization
> runs and hence enhance the overall efficiency of a SI simulation. Test
> load circuits are not needed for receiver models.
> Your comments regarding this topic are highly appreciated.

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