Re: [SI-LIST] : Terminating a bidirectional bus

D. C. Sessions ([email protected])
Mon, 03 May 1999 15:09:48 -0700

"Fox, Michael J" wrote:
>
> Arrigo,
> I'd recommend looking at FPGA and SRAM's DC requirements carefully. A
> series termination will cause a level shift. Unless you are using
> reflective-mode transmission or the buffers are internally terminated, I'd
> recommend parallel terminating both ends of the bus.
> But that's only good if both chips have the same DC requirements. If they
> have different DC requirements tell me about it and I'll give you that
> lecture.

All of the FPGAs that I've heard of have pure CMOS inputs with
pullups (if available) optional. So level shift shouldn't be an
issue. Also, the more complex ones give you the option of both
CMOS inputs (rational) vs TTL emulation (silly).

Actually, for a CMOS point-to-point connection you get surprisingly
good results with a single resistor in the center of the trace.

> -----Original Message-----
> From: Arrigo Benedetti [mailto:[email protected]]
> Sent: Monday, May 03, 1999 9:21 AM
> To: [email protected]
> Subject: [SI-LIST] : Terminating a bidirectional bus
>
> Dear all,
>
> I would like to know you opinion on this issue. I am interfacing a
> state of the art FPGA with a high speed synchronous SRAM device. Since
> the interface is bidirectional (the FPGA will read and write data to
> the memory) I was wondering what is is the best way to terminate this
> bus. My intuition is that if the data lines are not very long, then a
> series termination near the FPGA end could have an effect similar to a
> series termination near the memory end when the memory is driving the
> bus.
>
> I've in the the standard SI book, and haven't found any hint on the
> problem.
>
> thanks in advance
>
> -Arrigo Benedetti
> --
> Dr. Arrigo Benedetti e-mail: [email protected]
> Caltech, MS 136-93 phone: (626) 395-3695
> Pasadena, CA 91125 fax: (626) 795-8649
>
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-- 
D. C. Sessions
[email protected]


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