Hi,
Intel Corporation has an immediate opening for an entry level CAD
Engineer with Intel Test Tooling Operations in Santa Clara, California.
If you are qualified and interested in applying for this position, or
would like to refer someone who might be, please contact me at:
[email protected]
(408)-765-2619
Skills/Responsibilities: (official blurb)
Primarily responsible for the design of Sort Interface Unit's (SIU)
Printed Circuit Boards and Multi Layer Ceramic packages using Vendor
provided CAD tools which have been customized internally. Primary
interface to product groups to understand and negotiate design
requirements, SIU suppliers to provide design documentation and
clarification, and Sort site customers to provide on-line documentation
and clarify product issues. The candidate must be disciplined to
establish, follow and improve a process while being detail oriented to
ensure all issues are addressed. Strong communication skills necessary
to communicate with various groups. Experience with CAD tools usage and
customization on a UNIX or NT system and a basic background of electric
circuits and systems necessary. Programming in a high level language and
shell scripts a plus. B.S in Electrical or Computer Engineering
necessary.
My $.02:
Desire to build skills in physical design/ electrical design/ and
Signal/Power Integrity of PCB and Packaging technologies. Desire to
understand the entire design process from specification through,
physical design, simulation, verification while dealing with a diverse
customer base (all within Intel - product groups and HVM sites (fabs)).
Need strong analytical skills to come up to speed and understand/support
design activities quickly; and to be able to conceptualize very complex
three-dimensional structures in the design and explain them to others.
Once the current process is understood, you will need to develop methods
and algorithms to automate / improve the design process. Previous CAD
experience a big plus (SPICE, MDS and other simulation tools,
VLSI/PCB/package physical design). BTW an SIU is our TLA for the
interconnect between the die in wafer form, and an ATE tester.
For what it is worth, I found this department to be an exceptional entry
level position for myself. We work to develop a real diverse set of
skills in our new hires, and I have been able to experience a multitude
of skills and really focus on those that I was most interested in.
If you or someone you know is interested, please don't hesitate to
contact me.
Regards,
-Brett
--------------CA7D669B37A87FF843379822
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Description: Card for Brett Grossman
Content-Disposition: attachment; filename="vcard.vcf"
Content-Transfer-Encoding: 7bit
begin: vcard
fn: Brett Grossman
n: Grossman;Brett
org: Intel Test Tooling Operations
adr: 2200 Mission College Blvd;;MS: SC2-07;Santa Clara;CA;95052-8119;US
email;internet: [email protected]
title: Sr. Design Engineer
tel;work: (408)-765-2619
tel;fax: (408)-765-2518
x-mozilla-cpt: ;0
x-mozilla-html: TRUE
version: 2.1
end: vcard
--------------CA7D669B37A87FF843379822--
**** To unsubscribe from si-list: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****