RE: [SI-LIST] : Signal Polarities

Ingraham, Andrew ([email protected])
Thu, 22 Apr 1999 13:57:37 -0500

>I wonder if someone can briefly illustrate the pros and cons of using
>Active low signals versus Active High signals.
>- Form both views: a chip design and a board level design
>- From the Drivers technology selection.
>- From a Connection view:
> (a) in case of a piont to point connection.
> (b) multi-node connection.

With few exceptions, it makes little or no difference.

One exception is where several drivers can yank on a wire-OR signal, like an
interrupt line. Then active-low may be preferred for CMOS because available
open-drain outputs generally pull down; I don't know if there is a modern
technological preference for this. Maybe it's inherited from TTL where the
pulldown transistor was stronger. For ECL one would prefer active-high,
because NPN emitter followers only pull the output high.

Another case is where a bus uses terminators, pull-up, or pull-down
resistors, and is in one state more often than the other. If there are
pull-ups and 0's are more prevalent than 1's, you can save some power if
it's active low.

Long lines broken up with buffers, should have both active-low and
active-high sections, inverting once at each repeater. Otherwise asymmetry
would accumulate.


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