First off, you need to distinguish between full-swing differential
clocking and low-swing clocking. Low-swing differential signaling
using (for instance) current-steering logic is almost totally
insensitive to supply noise. Full-swing CMOS really doesn't matter
whether it's differential or single-ended.
> Assuming switching noise spikes are symmetrical in power and ground
> on-chip
> lines,
Bad assumption. Most on-chip supply noise results from IR drop
on the supply lines. Since a great deal of the (for instance)
rising edge signal current returns on the positive rail, the
ground paths are NOT disturbed as much as the positive rails.
Consider two adjacent drivers, A and B, driving across chip to
two adjacent receivers X and Y. A is a very strong driver into
a large net (let's say a data bus) B is a weaker driver into
a smaller net (a point-to-point clock path). A rises while B
falls. Because the falling edge of B introduces very little
current into the ground path and A is rising, the ground at the
drivers is largely undisturbed. The positive rail, OTOH, is
sucked way down. A third driver/receiver pair (C/Z) will be
delayed more on rising than on falling edges due to both gate
starvation and center point shift.
> they can be interpreted as a transient drop (or increase) in the
> power
> supply voltage of the gates connected to that noisy power supply lines.
Only if the gates are in fact driven rail-to-rail AND are not
driven with current-limited edge-control circuitry.
> If
> the two complementary last stages of the differential clock generator
> switch
> simultaneously with a transient drop in the power supply lines due to
> switching noise, both the true signal (i.e. raising) and the
> complementary
> clock signal (falling) will be slowed down. This means that the
> differential
> clock signal has an overall delay increase, compared with the case when
> no
> transient drop occurs simultaneously with the clock signal switching at
> the
> differential drivers. Thus, the switching noise induces clock jitter
> even if
> differential clock signaling is used.
True. Actually, it's even worse because the assymetrical disturbance
of the rails also shifts the crosspoint. What it really comes down to
is that full-swing CMOS can be complementary but not really differential.
> Has anybody experienced this or measured the effect of simultaneous
> switching
> noise on differential clock jitter?
Pretty standard stuff, actually. FWIW our internal studies show
that supply modulation of clock-path delays is the single largest
source of jitter in PLL-controlled synchronous logic.
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