Check the test conditions for the PCI spec. They are NOT the
conditions that a driver 'sees' in actual application. This
is a tragically common mistake -- people take data-sheet edge
rate figures and use them to get a false sense of security in
a signal-integrity situation.
Data-sheet formats and test loads have been handed down through
the generations. Archaeologist have found 45pf test loads in
cave drawings, and they're about as relevant today as the other
pictures of hunting wooly mammoths with rocks and spears.
Once again: look up the IBIS models for real drivers and check
the V/T tables into 50 ohms or less and 5pf or less.
> As for the Rambus channel example, the propagation Delay of 81.2
> ps/in resulted form the product:
> Delay = ( 2.9 pF/in )( 28 Ohms)
2.9 pf/in is true ONLY for 62-ohm microstriplines on FR4.
The invariant is velocity, capacitance depends on geometry.
> The 28 Ohms was obtained from a Rambus document and should be valid.
Actually it's a loaded-bus model. In any case it's a different
setup than the 2.9pf/in.
> The 2.9 pF/in was extracted from High-Speed Digital Design A Handbook of
> Black Magic, and now I feel that it is too low for Rambus channel
> computations.
Ah, that fine print!
> A recent publication states 200ps to 400 ps edge rates
> for Rambus bus. I have seen slower rise times in driver models furnished
> for Rambus simulations. Therefore, value of 400 ps was employed in this
> example.
There may well be slower RAMBUS parts -- it's been around since 800nm
or so. The question shouldn't be "how slow can RAMBUS drivers go" though,
it should be "how fast." The answer there is that internal noise sources
translate slow predriver edges into jitter, which RAMBUS does *not*
tolerate well. Therefore the designers keep the predriver edges quite
sharp, and the output follows. RAMBUS at a UI of 1250ps has, all in all,
faster edges than standard CMOS -- and standard CMOS in 250nm often
has edge rates down to 200ps.
The bottom line here is QUESTION YOUR ASSUMPTIONS. Keep in mind that
data sheets are, first and foremost, marketing documents. I shouldn't
have to say more.
> >----------
> >From: D. C. Sessions[SMTP:[email protected]]
> >Sent: Monday, March 29, 1999 12:54 PM
> >To: [email protected]
> >Subject: Re: [SI-LIST] : Critical Length
> >
> >Abe Riazi wrote:
> >
> >> Presented below is a numerical example, which utilizes Rise Time and
> >> Delay values within the PCI Bus specifications:
> >> Delay = 2.0 ns/ft
> >> Risetime = 1.5 ns
> >> Let k = 1/6, then:
> >> Critical Length = (1/6)(1.5 ns)/(2 ns/ft) = 1.5 Inches
> >
> >You're going to have a VERY hard time (outside of edge-rate controlled
> >stuff like USB) finding anything with an edge that slow.
> >
> >> Let us consider another example, selecting values applicable to the
> >> Rambus Channel:
> >> Delay = ( C )( Zo) = ( 2.9 pF/in)( 28 Ohms ) = 81.2 ps/in
> >> Rise Time = 400 ps
> >> Again letting k = 1/6, it follows:
> >> Critical Length = 0.821 Inches
> >> This result implies that trace segments and stubs smaller than 0.824
> >> inches are lumped, whereas those larger than 0.824 inches are classified
> >> as distributed. Such short critical lengths are often accompanied by
> >> numerous design and simulation challenges.
> >
> >Your numbers are off. 800ps/in is the speed of light in vacuum.
> >Actual PWB speeds range from about 160ps/in for microstrips to
> >almost 200ps/in for striplines. For RAMBUS, because of the noise
> >constraints and low impedance, you have to figure on stripline
> >with the consequent 190+ ps/in. Also, the edge rates are not
> >_minimum_ 400ps; IIRC that's the receiver-guaranteed-max.
> >
> >So figure on 250ps edges and 190 ps/in and you end up with an edge
> >in about 1.2 inches. That's a critical length at 1/6 of 200 mils,
> >not over 800.
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