Re: [SI-LIST] : A Question About Power Noise.

Scott McMorrow ([email protected])
Thu, 18 Mar 1999 23:36:12 -0800

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It seems to me that there is no one-answer-fits-all kind of solution.
However, normally we need to remember that the best high
frequency bypass capacitor on the board is the plane. At high
edge rates it is the on-chip capacitance which is most
effective, the plane which is next most effective, and then
the capacitor. We generally want to use the plane capacitance
as the primary high frequency bypass system.

There are cases where it may make sense to route directly
from a power pin to a capacitor to isolate noise to/from the
plane. This is certainly the case with analog circuitry. This then
increases the instantaneous voltage droop from the capacitor
to the power pin (ground also) in question. If there is enough
noise margin at the frequency of interest, then this is an
acceptable solution. However, the entire circuit must
be analyzed at the frequencies of interest to be sure.

The other interesting thing to remember is that we are dealing
with waves that have finite propagation velocities. The further
a decoupling element is from the circuit to be decoupled, the
longer it will take for the decoupling element to respond. This
is why dropping a via from the power and ground pins to the
planes is so effective. Ray Anderson talks of loop area. Another
way to "see" this is in terms of time of propagation to the
response element. Increased inductance, increases the response
time. Increased loop area increases the response time. The
net effect is a drop in the bandwidth of the decoupling system.

My two cents worth.


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